ESP-CV set constraint to output check

[davidpan]

I have a signal A and I would like to set constraint to the output (DO) check such that, for example, if in the symbolic cycle 1, A = 1, then I want to ignore output check for symbolic cycle 2 & symbolic 3, and only check the output at symbolic 4, else if in the symbolic cycle 1, A = 0 AND in the symbolic cycle 2, A = 1, then I want to ignore output check for symbolic cycle 3 & symbolic 4 , and only check the output at symbolic 5.

Is there a way to do it? If so how should I write the set_constraint command?

 

[BradtheRad]

This sounds like you could build it with logic gates. Or if you're writing code then a tree of IF-THEN statements.

Maybe flip-flops if you want a data signal to wait until the next clock cycle begins.

Make a flow-chart. A visual aid is more useful than lengthy verbal description.