ESD

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omar97

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Hello all,
I am using TSMC 65nm technology, I finished the design and when checking DRC thre is only one rule violated ESD.22g only on lowet left corner pad.
That is: width of the RPO on the drain side for PMOS >= 1

I can't understand what it is?
And how to solve it?
 

Learn to find and interpret the violation -> rule logic -> layout feature because this will be part of your life.

PDK layout groundrule package usually will have pages that show layout examples tied to any non-obvious rules. You should do that first if you are (as I) a visual person more than a coder.
 

Thank you for your advice
 

ESD.22g, if I remember correctly, is waivable. All TSMC pads do not pass ERC checks. Check the documentation that comes with the IP.
 

ThisIsNotSam said:
ESD.22g, if I remember correctly, is waivable. All TSMC pads do not pass ERC checks. Check the documentation that comes with the IP.
Click to expand...
In documentation, ESD on IO pads can be waivable but it is not state for corner pads.

I have ESD violations only on lower left pad, so I am not sure can I waive these violations?
 

Do you have a bond on top of the corner cell by any chance? Or a weird formed ring?
 

ThisIsNotSam said:
Do you have a bond on top of the corner cell by any chance? Or a weird formed ring?
Click to expand...
I have a ring of pads that containg IO pads, power pads, filler pads, and corner pads.

In future work we will add IO bonds.
 

That might be why the violation appears on the corner, because there is no bond cell. I am not sure.
 

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