omar97
Member level 1
Hello all,
I am using TSMC 65nm technology, I finished the design and when checking DRC thre is only one rule violated ESD.22g only on lowet left corner pad.
That is: width of the RPO on the drain side for PMOS >= 1
I can't understand what it is?
And how to solve it?
I am using TSMC 65nm technology, I finished the design and when checking DRC thre is only one rule violated ESD.22g only on lowet left corner pad.
That is: width of the RPO on the drain side for PMOS >= 1
I can't understand what it is?
And how to solve it?