ESD shock on frame ground causing FPGA problems

Hi There,

I have a pretty simple 4-layer board with strange ESD problems. Using a ESD gun and shocking the frame-ground terminal of the power terminal block the FPGA configuration will sometimes get corrupted. I'm stumped because, as far as I know, the goal of ESD protection is to get the charge to frame-ground which is what I'm doing but it still causes problems. I do have separate frame and digital ground which I tried connecting with caps or resistors with equally disappointing results

Any idea what could be causing this ?

Thanks in advance

/Dan

When you discharge that gun, you are also generating rf which might be inducing "bad" currents on your PCB. Just as an experiment, you might try shielding the board to see if that has any effect.

Hi Barry,

The board is already in an aluminum chassis, (slightly bigger than a VHS tape) with metal on all sides. The ESD is injected on the frame ground pin of the power terminal block on the rear panel. There are some openings on the front and rear panels for dip switches and connectors, which could in theory allow EMI to enter the board, but when when generating ESD nearby (not but connecting to) the product everything works ok, even without cover on. With the little knowledge I have about this that seems to indicate that its no a RF problem, but I'm certainly not sure. I can try covering up the holes with metal.

Other theory I have is that the ESD pulse comes in and causes problems through ground-bounce. I'm guessing that even though we have pretty good ground that 8KV 1ns pulse will generate some potential increase going into the unit. Not sure how to protect against that, other that somehow improving the grounding.

Thanks,

/Dan

Dan, I hate these problems; I feel your pain. You're right, it's probably not RF, I didn't realize this was already in a box. There is tons of stuff written about ESD protection, but it's all a little bit of black art; there don't seem to be any absolutes. What, exactly, is "frame ground", I'm not familiar with that term. Is it chassis ground? Is it connected to other 'grounds' in the system, or is it isolated? Do you have protection on all your I/O? That's a likely place for ESD to get in.

You have apparently an almost closed chasis, but you also have power supply and probably signals line crossing the chassis boundary. The ESD induced pulses are entering your circuit through this path. A separated frame ground doesn't necessarily help to block these interferences, the essential point is to suppress it at the board interface, for any external line.

Barry,

Previously I have comfortably been enjoying the predictability of digital designs (Verilog), but now I'm being thrown into ESD & Surge "black art". Quite frequently it doesn't make any noticeable difference adding TVS diodes or MOVs, which is very frustrating. If you know of any good books to read on this subject I would appreciate it.

With frame ground I'm referring to chassis ground. It can be connected to the main digital ground using caps or zero ohm resistors. Again, does not make much of a difference in our case unfortunately. Some I/O lines have external protection others we are relying on the internal. In this test case only power is connected though and we are shocking the chassis ground terminal of the power terminal block, so it would seem to me that I/O protection is not involved at this point although I could be wrong.

Thanks !

/Dan

Previously I have comfortably been enjoying the predictability of digital designs (Verilog), but now I'm being thrown into ESD & Surge "black art". Quite frequently it doesn't make any noticeable difference adding TVS diodes or MOVs, which is very frustrating. If you know of any good books to read on this subject I would appreciate it.

Click to expand...

Welcome to the world of real hardware design. Personally I have no specific literature suggestion but I hope others can help.

To lose the FPGA configuration, you either need to generate a sufficient large power supply spike or trigger the configuration pin. If external logic or a processor perform the configuration, they may be also affected by the ESD events. Without knowing the design details, we can only guess how this happens in your system.

I presume that your design has a continuous ground plane and all protection means will directly bleed off ESD surges to the ground plane.

FvM,

I agree with your analysis. I'm not sure how to suppress it at the board interface though. I have two 2.5cm wide islands of chassis-ground on the PCB's front and rear panel, with about 5mm separation from the main digital ground. These can be connected to the main ground using four 1812 caps or resistors. The ground layer and the top & bottom layer's copper pour all connect to the chassis ground, although the terminal block pin via has thermal reliefs on it so the terminal block only connects to the chassis ground using four 0.2mm wide traces. Not sure if that is a problem. For the next version I'm thinking about removing the chassis ground copper pour and make it a thick trace instead of having an entire polygon on the ground layer. I'm hoping that keeping the frame ground at a safe distance from other traces will help.

Does that sound like a good or bad idea ?

I appreciate your help

/Dan

ESD-wise, there's no big difference between using capacitive or direct connection of FG/PE and system ground, except for some series inductance introduced by the capacitors. It's usually required that through-plated pins use a thermal relief. It's hard to determine from a distance if there's a specific problem with the FG/PE terminal design. I still think that other external wires conduct the ESD surges. It's usually a matter of differential diagnostics to find the critical path, disconnecting and connecting individual wires and repeating the tests.

For anyone else seeing this type of issue I found this article online that does a pretty good job explaining what might be happening

**broken link removed**