I've seen some RFICs simply call it "somebody else's problem"
(which it was - mixers blow up at 10V HBM, the assembly house
had to really watch their step).
You can "go light" on handling ESD and accept some compromise
on various loss / distortion aspects, short of a "bulletproof" pin
protection.
Do not think so much about "nodes". Think about the current
loop through the part, and the voltage drops along the way,
which will impose difference voltages on everything along
the route. I like to model the ESD network comprehensively
to ensure complete "coverage". But that has entailed adding
capability to foundry PDKs, such as MOSFETs which have
a "live breakdown behavior" instead of just a flag, etc. And
that all depends from data which you'll have to take yourself,
using a TLP that you may have to make, yourself (I have).
The best ESD protection has zero resistance above trigger
and infinite below. A switched shunt is like this. A zener is not.
A MOSFET capable of handling an amp or more, is liable to
be bigger than your pass FET for 50 ohm systems and small
signal. For outputs you may be able to make the output FET
be its own protection (with attention paid to silicide pullbacks,
finger-end termination (flares / dogbones?) and so on. You
can expect pushback on anything you invent yourself, and
a few rounds of cut-and-try to select the layout that gives
both self-survivbility (the bare minimum of usefulness) and
effective protection of wimpy gate oxides.
A self-survivable GGNMOS can be a way to go, for "modest"
ESD protection in a star-ground arrangement. One with dense
body taps can give you a bidirectional protection (forward diode
below, MOS BV above). You want I-V data with varying width
(and pullback geometry, and...) to scale it for whatever ESD
threshold you negotiate.