An alternative is to do something like on-chip ESD protection.
A plurality of forward-clamp diodes from Gnd to line, from line
to a VESD rail (which might or might not be 3.3V - LVDS has
only about 2V max).
Now put a fat zener from that ESD rail to local GND, and a fat
cap for filtering, and that VESD will be about 2.6V pumped by
3.3V, and all the forward diodes (except that one) will be
reverse biased all the time, but ready to dump overrange
currents into either Gnd or VESD.
Now you only care about the central zener, for conduction
qualities, and you care very little about the diodes - though
you do want adequate pulsed current capacity, and at the
threat current level, no more than maybe 2V forward, and all
that at your <=5pF. This is a well bounded component selection
problem, to solve by tedious inspection of parts tables.