Clamping to 12V may suffice to protect logic inputs,
there is a "gap" between abs max pin rating in the
datasheet and what happens at ESD-pulse timescales
(e.g. short-pulse BVox is always 2X or more than
quasi-DC, ramp-to-current BVox in my experience).
Liable to be a better answer for "5V" inputs, than
"1.2V" LVDS running off a 1.8V I/O rail (with gate
BVox running maybe 4V).
But if it were me, I'd be checking the TVS and serial
lines on some test-to-fail victim boards with my own
TLP or a proper ESD pin-pin tester just to see where
things really do fail.