esd circuit simulation ... critical or not?...

Is it possible to design a circuit ESD protection using only as HSPICE circuit simulator?. If so, what model is best suited to perform simulations and obtain approximate results? Also, what are the most relevant parameters of this model. I've been reading some papers on this subject and I am still a little disoriented.

Thanks.

:?:

I have had pretty reasonable results from it, although you
might need some work to determine the real fail thresholds,
voltage and current per exposed device / feature, to work and
criticize against. And many foundries do not model, well or at
all, things like device breakdown voltage / resistance /
snapback.

You can make a nice simple ESD "stinger" with a pulsed
voltage source stepping from 0 to vESD in a nS, series
cap and resistor same values as the HBM (and/or others).

Then you get to enjoy the tedium of trying out all pin-pin
paths. Woo-hoo!

Most transistor models - I know of none - do not include high- voltage/current characterization (as needed for an ESD event simulation). For the circuit designer the best strategy is to understand and carefully follow the ESD protection architecture used by the company .

I have worked with the MOS transistor compact model, but I need help with the simulation and model selection.
:|

Most likely you will have to "supplement" the foundry PDK
with some hand-fitted models. I've done this with zener and
resistor elements (lvsIgnore='t') hand fitted to TLP 'scope
data (transmission line pulser, simulating ESD). I had to
build the TLP myself, used a spool of coax, a 100K feed
resistor, a 39-ohm output resistor (trying to get roughly
50 ohms total loop, including the clamps under test) and a
mercury wetted relay. A 1 ohm sense resistor in the return
and two 'scope probes will give you the I, V data you need.
I is voltage across the sense resistor, V is differential
voltage across the part. Drive the relay and trigger the 'scope
with a standard pulse generator.

To get 100V I had to stack every supply in the lab, but a
Variac and rectifiers would do as well. Without the HBM
series resistor you should be able to get past a couple
of amps, equating to a couple of kV ESD threat (kV = amps*1.5Kohm).

The models are required for ESD simulation, these models directly come from the foundry. These models simulates the high voltage behavior of the MOS transistors and diodes. In case of High voltage the parasitic of MOS transistors i.e. drain/source substrate diode or pnp/npn structure gets activated. You can simulate if you include parasitic elements in your model and apply the general trend of high voltage impact on bipolar and diodes.
Thanks

Don't bet on foundry models representing anything beyond
"recommended application" operating points. If they do, that's
way better than my experience (and I have used a lot of
processes though not that many at pure-play foundries).

Read the fine print, and try some simulations to see if you
ever get a sensible appearing breakdown I-V result.

If not, the rest of the journey is on you....

dick_freebird said:

............ I had to
build the TLP myself,...........

Click to expand...

hi, dick_freebird
you built a TLP test system by yourself? wow~~~
DIY is not cheap either, right?
i want to DIY one, too
seems very tough