ESD.10g error in Cell in cadence layout

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Hi everone
i am facing DRC errors such as ESD.10g in cadence layout using 0.18um tsmc library. how to address this error. i have attached the image for reference.
 

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Same as anything else. Go to the DRC rules deck, find the rule tag
and then deduce what its logic is on about. You may also find in
the "paper" groundules a cross-reference to rule-number (if it's
a well built PDK) with pictures.
 

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dick_freebird said:
Same as anything else. Go to the DRC rules deck, find the rule tag
and then deduce what its logic is on about. You may also find in
the "paper" groundules a cross-reference to rule-number (if it's
a well built PDK) with pictures.
Click to expand...
thanks for replying, and for reference, i have shared the DRC rule, Could you suggest me what to do
 
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Note that I said -you- must deduce. I did not volunteer.

I have no idea what OD means here. Lots of process
specific jargon. That's for you to understand, read the
design manual that's somewhere in the PDK install.

Might start with the ESD rules section. Some stuff about
pad-to-pad devices, which are a for-sure ESD threat,
might apply or not as the larger context and the
error-flag-polygon are not shown (or not obvious, for
fill code or line-on-line).
 

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OD = active

this being TSMC, it is highly possible this ESD rule can be waived or is a false positive. read the documentation that comes with the IO cell library. sometimes there is a PDF or a tiny readme.txt file that list all the limitations of the library. ESD rules are very typically listed in these files as *ignore*
 

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