Errors during verilog code synthesis

Hi, I am implementing a verilog code for UART in my code but every time I synthesize it, I get the following error:

ERROR:Xst:528 - Multi-source in Unit <test> on signal <data_out>; this signal is connected to multiple drivers.

The code for UART is pretty lengthy and I think that the problem lies in the following part:


always @(negedge clk or negedge rst_n)
begin
if(~rst_n)
ser_out <= 1'b1;
else
begin
case({start_bit_sig,data_bits_sig,stop_bit_sig})
3'b100: ser_out <= 1'b0;
3'b010: ser_out <= data_buf[0];
3'b001: ser_out <= 1'b1;
default: ser_out <= 1'b1;
endcase
end
end


Someone please help me in solving this problem. I will be very thankful.

Thank You for any help from anyone.