ic5141 license 2009
[icer@RHEL4 license]$ /eda/toos/bin/Imgrd -c license.dat
-bash: /eda/toos/bin/Imgrd: 没有那个文件或目录
but
[icer@RHEL4 license]$ cd /eda/tools/bin
[icer@RHEL4 bin]$ ls -a
. hierEditor tdmintegrate
.. histogram tdmintegrate.main
32bit ilmail tdmlinkreflib
64bit instdir tdmlistdir
ccpCtfUpdtr lbsrun tdmloadrelease
ccpDfIICatUpdtr lic_error tdmloadrelease.main
ccpHdbUpdtr lmCheckExpiration.cds tdmloadtpl
ccpVerilogUpdtr lmCheckExpiration.pl tdmlockfile
ccpVhdlUpdtr lmdiag tdmls
cdsCopyShell lmdown tdmMailScript
cdsdoc lmgrd tdmmergebaseir
Added after 40 minutes:
Lmgrd not Imgrd,but....
[icer@RHEL4 license]$ /eda/tools/bin/lmgrd -c license.dat
Incorrectly built binary which accesses errno or h_errno directly. Needs to be fixed.
[icer@RHEL4 license]$ 13:03:14 (lmgrd) -----------------------------------------------
13:03:14 (lmgrd) Please Note:
13:03:14 (lmgrd)
13:03:14 (lmgrd) This log is intended for debug purposes only.
13:03:14 (lmgrd) There are many details in licensing policies
13:03:14 (lmgrd) that are not reported in the information logged
13:03:14 (lmgrd) here, so if you use this log file for any kind
13:03:14 (lmgrd) of usage reporting you will generally produce
13:03:14 (lmgrd) incorrect results.
13:03:14 (lmgrd)
13:03:14 (lmgrd) -----------------------------------------------
13:03:14 (lmgrd)
13:03:14 (lmgrd)
13:03:14 (lmgrd) FLEXlm (v8.4a) started on RHEL4 (linux) (8/22/2009)
13:03:14 (lmgrd) Copyright (c) 1988-2003 by Macrovision Corporation. All rights reserved.
13:03:14 (lmgrd) US Patents 5,390,297 and 5,671,412.
13:03:14 (lmgrd) World Wide Web: **broken link removed**
13:03:14 (lmgrd) License file(s): license.dat
13:03:14 (lmgrd) lmgrd tcp-port 5280
13:03:14 (lmgrd) Starting vendor daemons ...
13:03:14 (lmgrd) Started cdslmd (internet tcp_port 32952 pid 28833)
Incorrectly built binary which accesses errno or h_errno directly. Needs to be fixed.
13:03:14 (cdslmd) FLEXlm version 8.4a
13:03:15 (cdslmd) Server started on RHEL4 for: 100
13:03:15 (cdslmd) 111 11400 12141
13:03:15 (cdslmd) 12500 14000 14010
13:03:15 (cdslmd) 14020 14040 14101
13:03:15 (cdslmd) 14111 14120 14130
13:03:15 (cdslmd) 14140 14410 200
13:03:15 (cdslmd) 20120 20121 20122
13:03:15 (cdslmd) 20123 20124 20127
13:03:15 (cdslmd) 20128 20220 20221
13:03:15 (cdslmd) 20222 20227 206
13:03:15 (cdslmd) 207 21060 21200
13:03:15 (cdslmd) 21400 21900 21920
13:03:15 (cdslmd) 22650 22800 22810
13:03:15 (cdslmd) 24015 24025 24100
13:03:15 (cdslmd) 24205 250 251
13:03:15 (cdslmd) 26000 274 276
13:03:15 (cdslmd) 279 283 300
13:03:15 (cdslmd) 305 312 314
13:03:15 (cdslmd) 316 318 32110
13:03:15 (cdslmd) 32140 32150 32190
13:03:15 (cdslmd) 322 32500 32501
13:03:15 (cdslmd) 32502 32510 32550
13:03:15 (cdslmd) 32600 32610 32620
13:03:15 (cdslmd) 32630 32640 32760
13:03:15 (cdslmd) 33010 33301 334
13:03:15 (cdslmd) 336 34500 34510
13:03:15 (cdslmd) 365 370 371
13:03:15 (cdslmd) 37100 373 40020
13:03:15 (cdslmd) 40030 40040 40500
13:03:15 (cdslmd) 41000 50000 50010
13:03:15 (cdslmd) 501 50110 50200
13:03:15 (cdslmd) 51022 51023 51060
13:03:15 (cdslmd) 51070 51170 550
13:03:15 (cdslmd) 570 61300 61400
13:03:15 (cdslmd) 71110 71120 71130
13:03:15 (cdslmd) 920 940 945
13:03:15 (cdslmd) 950 960 963
13:03:15 (cdslmd) 964 965 966
13:03:15 (cdslmd) 972 974 991
13:03:15 (cdslmd) 994 995 ABIT
13:03:15 (cdslmd) ALL_EBD AMD_MACH ANALOG_WORKBENCH
13:03:15 (cdslmd) AWB_BEHAVIOR AWB_Batch AWB_DIST_SIM
13:03:15 (cdslmd) AWB_MAGAZINE AWB_MAGNETICS AWB_MIX
13:03:15 (cdslmd) AWB_PPLOT AWB_RESOLVE_OPT AWB_SIMULATOR
13:03:15 (cdslmd) AWB_SMOKE AWB_SPICEPLUS AWB_STATS
13:03:15 (cdslmd) Actel_FPGA Advanced_Cell_Placer Advanced_Package_Designer
13:03:15 (cdslmd) Affirma_AMS_distrib_processing Affirma_NC_Simulator Affirma_NC_VHDL_Desktop_Sim
13:03:15 (cdslmd) Affirma_RF_IC_package Affirma_RF_SPW_model_link Affirma_advanced_analysis_env
13:03:15 (cdslmd) Affirma_equivalence_checker Affirma_sim_analysis_env Allegro_CAD_Interface
13:03:15 (cdslmd) Allegro_Designer Allegro_PCB_Interface Altera_MAX
13:03:15 (cdslmd) Ambit_BuildGates Ambit_libcompile Artist_Optimizer
13:03:15 (cdslmd) Artist_Statistics Atmel_ATV BOGUS
13:03:15 (cdslmd) Base_Digital_Body_Lib Base_Verilog_Lib BlockMaster_Characterizer
13:03:15 (cdslmd) BlockMaster_Optimizer BoardQuest_Team BuildGates_Extreme
13:03:15 (cdslmd) CELL3 CELL3_ARO CELL3_CROSSTALK
13:03:15 (cdslmd) CELL3_CTS CELL3_ECL CELL3_OPENDEV
13:03:15 (cdslmd) CELL3_OPENEXE CELL3_PA CELL3_PR
13:03:15 (cdslmd) CELL3_QPLACE_TIMING CELL3_SCAN CELL3_TIMING
13:03:15 (cdslmd) CELL3_WIDEWIRE CP_Ele_Checks CPtoolkit
13:03:15 (cdslmd) CWAVES CWB01 CWB03
13:03:15 (cdslmd) CWB04 CWB05 CheckPlus
13:03:15 (cdslmd) Clock_Tree_Generation Cobra_Simulator ComposerCheckPlus_AdvRules
13:03:15 (cdslmd) ComposerCheckPlus_Checker ComposerCheckPlus_RuleDev Composer_EDIF300_Connectivity
13:03:15 (cdslmd) Composer_EDIF300_Schematic Composer_Spectre_Sim_Solution ConcICe_Option
13:03:15 (cdslmd) Corners_Analysis DISCRETE_LIB DRAC2CORE
13:03:15 (cdslmd) DRAC2DRC DRAC2LVS DRAC3CORE
13:03:15 (cdslmd) DRAC3DRC DRAC3LVS DRACACCESS
13:03:15 (cdslmd) DRACDIST DRACERC DRACLPE
13:03:15 (cdslmd) DRACLVS DRACPG_E DRACPLOT
13:03:15 (cdslmd) DRACPRE DRACSLAVE Datapath_Preview_Option
13:03:15 (cdslmd) Datapath_VHDL Datapath_Verilog Device_Level_Placer
13:03:15 (cdslmd) Device_Level_Router Distributed_Dracula_Option EBD_edit
13:03:15 (cdslmd) EBD_floorplan EBD_power EDIF_Netlist_Interface
13:03:15 (cdslmd) EDIF_Schematic_Interface EMCdisplay EMControl
13:03:15 (cdslmd) Envisia_GE_ultra_place_route Envisia_PKS Envisia_RAC
13:03:15 (cdslmd) Envisia_Utility Envisia_LowPower_option Envisia_DataPath_option
13:03:15 (cdslmd) Envisia_SE_ultra_place_route Extended_Digital_Body_Lib Extended_Digital_Lib
13:03:15 (cdslmd) Extended_Verilog_Lib FPGA_Flows FPGA_OPTIMIZER
13:03:15 (cdslmd) FPGA_Tools FUNCTION_LIB Framework
13:03:15 (cdslmd) GATEENSEMBLE GATEENSEMBLE_ARO GATEENSEMBLE_CROSSTALK
13:03:15 (cdslmd) GATEENSEMBLE_CTS GATEENSEMBLE_CTS_LE GATEENSEMBLE_CTS_UL
13:03:15 (cdslmd) GATEENSEMBLE_ECL GATEENSEMBLE_LOWEND GATEENSEMBLE_OPENDEV
13:03:15 (cdslmd) GATEENSEMBLE_OPENEXE GATEENSEMBLE_PA GATEENSEMBLE_PR_LE
13:03:15 (cdslmd) GATEENSEMBLE_PR_UL GATEENSEMBLE_QPLACE_TIMING GATEENSEMBLE_SCAN
13:03:15 (cdslmd) GATEENSEMBLE_TIMING GATEENSEMBLE_TIMING_LE GATEENSEMBLE_TIMING_UL
13:03:15 (cdslmd) GATEENSEMBLE_UNLIMITED GATEENSEMBLE_WIDEWIRE Gate_Ensemble_DSM
13:03:15 (cdslmd) Gate_Ensemble_DSM_Crosstalk Gate_Ensemble_WARP HDL-DESKTOP
13:03:15 (cdslmd) IC_Inspector IC_autoroute IC_edit
13:03:15 (cdslmd) IC_hsrules IDF_Bi_Directional_Interface LAS_Cell_Optimization
13:03:15 (cdslmd) LEAPFROG-BV LEAPFROG-CV LEAPFROG-SLAVE
13:03:15 (cdslmd) LEAPFROG-SV LEAPFROG-SYS LID10
13:03:15 (cdslmd) LID11 LINEAR_LIB LSE
13:03:15 (cdslmd) MAG_LIB MIXAD_LIB Model_Check_Analysis
13:03:15 (cdslmd) NCSim_Desktop NCVLOG_CGOPTS NC_Verilog_Compiler
13:03:15 (cdslmd) NC_Verilog_Data_Prep_Compiler NC_Verilog_Simulator NC_VHDL_Simulator
13:03:15 (cdslmd) NC-simulator Nihongoconcept OASIS_Simulation_Interface
13:03:15 (cdslmd) OpenModeler_SFI OpenModeler_SWIFT OpenSim
13:03:15 (cdslmd) OpenWaves PICDesigner PIC_Utilities
13:03:15 (cdslmd) PLD PWM_LIB Pearl
13:03:15 (cdslmd) Pearl_Cell Placement_Based_Synthesis Prevail_Board_Designer
13:03:15 (cdslmd) Prevail_Correct_By_Design Prevail_Designer Preview_Synopsys_Interface
13:03:15 (cdslmd) QPlace Quickturn_Model_Manager RapidPART
13:03:15 (cdslmd) SWIFT Schematic_Generator SigNoiseCS
13:03:15 (cdslmd) SigNoiseEngineer SigNoiseExpert SigNoiseStdDigLib
13:03:15 (cdslmd) Signal_Integrity SiliconQuest SiliconQuest_CTGen_Option
13:03:15 (cdslmd) Silicon_Ensemble Silicon_Ensemble_CTS Silicon_Ensemble_DSM
13:03:15 (cdslmd) Silicon_Ensemble_DSM_Crosstalk Silicon_Ensemble_OpenDev Silicon_Ensemble_OpenExe
13:03:15 (cdslmd) Silicon_Ensemble_WARP Silicon_Synthesis_QPBS SimControl
13:03:15 (cdslmd) SimVision SpectreBasic SpectreRF
13:03:15 (cdslmd) Spectre_BTAHVMOS_Models Spectre_BTASOI_Models Spectre_NorTel_Models
13:03:15 (cdslmd) Spectre_ST_Models Substrate_Coupling_Analysis Synlink_Interface
13:03:15 (cdslmd) UET ULMdelta ULMecho
13:03:15 (cdslmd) ULMhotel ULMindia ULMjuliette
13:03:15 (cdslmd) ULMmike Universal_Smartpath VERILOG-SLAVE
13:03:15 (cdslmd) VERILOG-XL VERITIME VHDLLink
13:03:15 (cdslmd) VHDL_desktop VXL-ALPHA VXL-LMC-HW-IF
13:03:15 (cdslmd) VXL-SWITCH-RC VXL-TURBO VXL-VCW
13:03:15 (cdslmd) VXL-VET VXL-VLS VXL-VRA
13:03:15 (cdslmd) Vampire_HDRC Vampire_HLVS Vampire_MP
13:03:15 (cdslmd) Vampire_RCX Vampire_UI Verif_Ckpit_Analysis_Env
13:03:15 (cdslmd) Verilog_XL_Turbo_NT Verilog_XL_Desktop Verilog_desktop
13:03:15 (cdslmd) Virtuoso_Schem_Option Virtuoso_XL Xilinx_FPGA
13:03:15 (cdslmd) a2dxf aae-signalscan aae-signalscan-transaction
13:03:15 (cdslmd) aae-transaction-explorer actomd affirma-signalscan
13:03:15 (cdslmd) affirma-signalscan-control affirma-signalscan-pro affirma-signalscan-schmatic
13:03:15 (cdslmd) affirma-signalscan-source affirma-signalscan-transaction affirma-transaction-explorer
13:03:15 (cdslmd) allegro_dfa allegro_dfa_att allegro_non_partner
13:03:15 (cdslmd) allegro_symbol allegroprance archiver
13:03:15 (cdslmd) arouter caeviews cals_out
13:03:15 (cdslmd) catia cbds_in cdxe_in
13:03:15 (cdslmd) comp compose compose_autoplan
13:03:15 (cdslmd) compose_gcr compose_scells compose_tlmr
13:03:15 (cdslmd) compose_util concept conceptXPC
13:03:15 (cdslmd) cpe cpte crefer
13:03:15 (cdslmd) cvtomd debug dfsverifault
13:03:15 (cdslmd) dracula_in dxf2a e2v
13:03:15 (cdslmd) edif2ged expgen fethman
13:03:15 (cdslmd) fetsetup fluke fsim
13:03:15 (cdslmd) gbom ged2edif glib
13:03:15 (cdslmd) gloss gphysdly gscald
13:03:15 (cdslmd) gspares hp3070 iges_electrical
13:03:15 (cdslmd) intrgloss intrroute intrsignoise
13:03:15 (cdslmd) ipc_in ipc_out lwb
13:03:15 (cdslmd) mdin mdout mdtoac
13:03:15 (cdslmd) mdtocv multiwire packager
13:03:15 (cdslmd) pcb_editor pcb_engineer pcb_interactive
13:03:15 (cdslmd) pcb_prep pcb_review pcomp
13:03:15 (cdslmd) placement plotVersa ptc_in
13:03:15 (cdslmd) ptc_out quanticout redifnet
13:03:15 (cdslmd) rt sdrc_in sdrc_out
13:03:15 (cdslmd) signoise skillDev stream_in
13:03:15 (cdslmd) stream_out swap sx
13:03:15 (cdslmd) synSmartIF synSmartLib synTiOpt
13:03:15 (cdslmd) tsTSynVHDL tsTSynVLOG tsTestGen
13:03:15 (cdslmd) tsTestIntf tune tw01
13:03:15 (cdslmd) tw02 v2e vc-signalscan
13:03:15 (cdslmd) vc-signalscan-transaction vc-transaction-explorer verifault
13:03:15 (cdslmd) vgen viable visula_in
13:03:15 (cdslmd) vloglink wedifsch xilCds
13:03:15 (cdslmd) xilComposerFE xilConceptFE xilEdif
13:03:15 (cdslmd) TimingAnalysis RCExtraction DelayCal
13:03:15 (cdslmd) TrialRoute AmoebaPlace DesignViewer
13:03:15 (cdslmd) Route CeltIC SignalIntegrity
13:03:15 (cdslmd) ClockSyn PowerAnalysis SpecialRoute
13:03:15 (cdslmd) TimingBudget PartitionOptimizer FirstEncounter
13:03:15 (cdslmd) FirstEncounterSOC FE_Classic FE_Ultra
13:03:15 (cdslmd) SOC_Encounter Encounter_C Envisia_SE_SI_place_route
13:03:15 (cdslmd) NanoRoute_Ultra Nano_Encounter Multithread_Route_Option
13:03:15 (cdslmd) Cierto_SPW_comm_library_fxp_pt Cierto_HW_design_sys_2000 Cierto_SPW_multimedia_kit
13:03:15 (cdslmd) Cierto_SPW_GSM_VE Cierto_SPW_IS136_VE Cierto_SPW_pcscdma_VE
13:03:15 (cdslmd) Cierto_signal_proc_wrksys_2000 Cierto_SPW_comm_lib_flt_pt SPW_Smart_Antenna_Library
13:03:15 (cdslmd) Cierto_Wireless_LAN_Library Cierto_SPW_CDMA_Library Cierto_SPW_model_manager
13:03:15 (cdslmd)
13:03:15 (cdslmd) All FEATURE lines for this vendor behave like INCREMENT lines
13:03:15 (cdslmd)
Added after 2 hours 40 minutes:
the first question was solved,thank
i have another question:
[icer@RHEL4 ~]$ icfb&
[1] 20460
[icer@RHEL4 ~]$ Xlib: connection to ":0.0" refused by server
Xlib: No protocol specified
*ERROR* X Window Display Initialization failure
*WARNING* X Window Display Initialization failure