Error: Zero-time oscillation in node

[ERIC.C]

Dear Friends,

Can someone please advice what's wrong with my code? I found this error when I run the functional simulation. Error: Zero-time oscillation in node

Below is my code.

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Code VHDL - [expand]
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity Lab6_Synchronous_5bit_enable_up_down_counter is
port ( Clock, Enable, UpDn, Rst :in std_logic;
       Output                   :out std_logic_vector(4 downto 0));
 
end Lab6_Synchronous_5bit_enable_up_down_counter;
       
architecture Synchronous_5bit_enable_up_down_counter of Lab6_Synchronous_5bit_enable_up_down_counter is   
 
signal count:std_logic_vector(4 downto 0); 
signal s : std_logic;
begin 
s<= Enable and Clock; 
process (Clock, UpDn)
begin 
if rst = '1' then
count <= "00000";
elsif s='1' then 
if UpDn = '1' then 
count <= count+1;
else 
count <= count-1;
end if;         
else 
count <= count; 
end if;
end process;
output <=count; 
end Synchronous_5bit_enable_up_down_counter;

---

 

[std_match]

You forgot the "if rising_edge(Clock)".

Edit:
I recommend that you start using the numeric_std library instead of std_logic_unsigned.
This means that "count" will be of type unsigned instead of std_logic_vector.

 

[SynthWorks]

What you coded is a latch that is enabled by your gating circuit "Enable and Clock".

What you need is a flip-flop that activates on the rising edge of clock. In addition, you do not want to use a clock gate ("Enable and Clock"), but instead want to do a data path enable. The following is the template you need.

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Code VHDL - [expand]
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process (rst, Clock)
begin 
  if rst = '1' then
    count <= "00000";
  elsif rising_edge(Clk) then
    if Enable ='1' then           -- note enable coded separate from clock to ensure synthesis tool support 
      -- Do your counter stuff here
    end if ;
  end if; 
end process ;

---

Note, if you have a proper flip-flop, you do not need the final else with the assignment "count <= count".

 

[ERIC.C]

Hi std_match:

Thanks for your input. After add in "if rising_edge(Clock)" I'm able to run the functional simulation but I can't get the result for timing simulation. There output is 0.

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Code VHDL - [expand]
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity Lab6_Synchronous_5bit_enable_up_down_counter is
port ( Clock, Enable, UpDn, Rst :in std_logic;
       Output                   :out std_logic_vector(4 downto 0));
 
end Lab6_Synchronous_5bit_enable_up_down_counter;
       
architecture Synchronous_5bit_enable_up_down_counter of Lab6_Synchronous_5bit_enable_up_down_counter is   
 
signal count:std_logic_vector(4 downto 0); 
signal s : std_logic;
begin 
s<= Enable and Clock; 
process (Clock, UpDn)
begin 
if rising_edge(clock) then
if rst = '1' then
 
count <= "00000";
 
elsif s='1' then
  
if UpDn = '1' then 
count <= count+1;
else 
count <= count-1;
end if;       
else 
count <= count; 
end if;
end if;
end process;
output<=count;
end Synchronous_5bit_enable_up_down_counter;

---

 

[ads-ee]

you didn't take synthworks advice and still have the following in your code:

s<= Enable and Clock;
elsif s='1' then

This is a race condition in the code between the clock edge and generating an enable in the code based on the clock and the Enable signal. Scheduling wise I think the rising_edge(clock) happens before the transition on s is ever seen.

You also have UpDn in your sensitivity list, which it shouldn't be as it's inside the rising_edge(clock) if statement.

Maybe you need to go back and read up on how to code a process.

Regards