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Re: error: Xst:899 in verilog code synthesis..FF or Latch t
it solved my above prob
i have few more questions about the code given below
1) on simulating this code s21 gives 32'b 10101010101010101010101010101010 when ins==0 and gives 32'b 01010101010101010101010101010101 when ins==1
however it should be vice versa as given in code ...why is it so??
2) s21 then goes to inp which is a serial to parallel shiftreg but only a few bits are shifted properly into it at every clock edge and after that the waveform flattens out whereas it should show shifting of all bits properly...how could it be corrected?
3) when i implemented this code it gave following errors:
Total Number of 4 input LUTs: 7 out of 9,312 1%
Number used as logic: 6
Number used as Shift registers: 1 Number of bonded IOBs: 2,084 out of 232 898% (OVERMAPPED) IOB Flip Flops: 987 Number of bonded Out/Bidir IOBs: 2,080 out of 176 1181% (OVERMAPPED) Number of bonded Input IBUFs: 4 out of 56 12%
Number of GCLKs: 2 out of 24 8%
always@ ( posedge outclk or posedge clr)
begin
#0.1;
if (clr)
out1<=0;
else
begin
{out1[1023:b]}<={out[1023-b:0]};
{out1[c:0]}<={out[1023:1023-c]};
end
end
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