error whilt using for generate

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rashmi.imhsar

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error while using "for generate"

I want to run the two components one after the other , for 15 times. the for generate is showing the following errors:

** Error: Nonresolved signal 'led' has multiple sources.

** Error: Nonresolved signal 'q_main' has multiple sources.

** Error: VHDL Compiler exiting

Here is my code:
--
-- A 4-bit Linear feedback shift-register (LFSR)-PRBS & BERT.
--
-- ----------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

-- ----------------------------------------------------------------

entity lfsr4_txrrxr is
port
(
rstN_main : in std_logic;
clk_main : in std_logic;

-- Load the LFSR register
load_main : in std_logic;


-- transmitter LFSR seed value (eg, 0001)
--seed1 : in bit_vector(3 downto 0);


-- Enable the LFSR register
enable_main : in std_logic;

-- LFSR register (1-bit of this is the PRBS signal)
led : out bit_vector(3 downto 0)

);
end entity;

-- ----------------------------------------------------------------

architecture basic of lfsr4_txrrxr is
-- Internal LFSR register
signal data, data02 : bit_vector(3 downto 0);
signal seed : bit_vector(3 downto 0):="0001";
signal n : integer:=0;
signal q_main : bit_vector(3 downto 0);


component lfsr4 is
port (
rstN : in std_logic;
clk : in std_logic;

-- Load the LFSR register
load : in std_logic;


-- transmitter LFSR seed value (eg, 0001)
seed1 : in bit_vector(3 downto 0);


-- Enable the LFSR register
enable : in std_logic;


-- LFSR register (1-bit of this is the PRBS signal)
--data : inout bit_vector(3 downto 0);
q : inout bit_vector(3 downto 0)

);

end component;

component rxr4 is
port (
rstN : in std_logic;
clk : in std_logic;

-- Load the LFSR register
q : in bit_vector(3 downto 0);

-- LFSR register (1-bit of this is the PRBS signal)
led : out bit_vector(3 downto 0)

);
end component;

begin

l1: for i in 1 to 15 generate

p1: lfsr4 port map
(
rstN => rstN_main,
clk => clk_main,
load => load_main,
seed1 => seed,
enable => enable_main,
q => q_main

);

p2: rxr4 port map
(
rstN => rstN_main,
clk => clk_main,
q => q_main,
led => led

);

end generate l1;
end architecture;
 
Last edited:

Next time please use syntax tags, when posting your code.

You are trying to short 15 copies of led output together. The generate statement is creating 15 copies of the lfsr4 and rxr4 components with identical connections. What are you trying to accomplish with this code?
e.g.
Code VHDL - [expand]
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-- unraveling the generate produces...
  p1_1: lfsr4 port map 
  (
    rstN => rstN_main,
    clk => clk_main,
    load => load_main,
    seed1 => seed,
    enable => enable_main,
    q => q_main
  );
  p1_2: lfsr4 port map 
  (
    rstN => rstN_main,
    clk => clk_main,
    load => load_main,
    seed1 => seed,
    enable => enable_main,
    q => q_main
  );
-- ...
  p1_15: lfsr4 port map 
  (
    rstN => rstN_main,
    clk => clk_main,
    load => load_main,
    seed1 => seed,
    enable => enable_main,
    q => q_main
  );
 
  p2_1: rxr4 port map 
  (
    rstN => rstN_main,
    clk => clk_main,
    q => q_main,
    led => led
  );
  p2_2: rxr4 port map 
  (
    rstN => rstN_main,
    clk => clk_main,
    q => q_main,
    led => led
  );
-- ...
  p2_15: rxr4 port map 
  (
    rstN => rstN_main,
    clk => clk_main,
    q => q_main,
    led => led
  );

Can you now see how this is a problem....

Explain what you want as a result of the 15 copies and perhaps then a correction to your code can be suggested. Without knowing what you are trying to do all I can suggest is to make the led output of lfsr4_txrxr an array with 15 4-bit bit_vectors and then use led =>led(i) in your instantiation. Same thing applies to the q => q_main(i) for both p1 & p2 instances.

I also noticed you are using inout for q, you shouldn't be doing that unless it's an I/O pin and you have an actual bidirectional pin. As written lfsr4's q port should be defined as an out

regards
 
Last edited:
Re: error while using for generate

Sorry I understand its difficult to help without giving proper inputs.

How do I attach my code ?I could not find syntax tags icon anywhere !

Here is the code of the two components. Basically I want to send a 4 bits from a 4 bit lfsr and receive the 4 bits. A 4 bit lfsr is used at the receiver also to compare the last bit of the generated output (from rxr lfsr) and the received 4 bits.

After comparing, the control should be transferred to the Txr to send the next 4 bits to the RXr. This way, I want to compare 15 bits and so the iteration should be for 15 times.

The error value is displayed using LEDs after 15 iterations are over. So I do not need to store the LED values in an array.



TXR CODE:

library ieee;
use ieee.std_logic_1164.all;

-- ----------------------------------------------------------------

entity lfsr4 is
port (
rstN : in std_logic;
clk : in std_logic;

-- Load the LFSR register
load : in std_logic;


-- transmitter LFSR seed value (eg, 0001)
seed1 : in bit_vector(3 downto 0);


-- Enable the LFSR register
enable : in std_logic;


-- LFSR register (1-bit of this is the PRBS signal)
--data : inout bit_vector(3 downto 0);
q : inout bit_vector(3 downto 0)


);

end entity;

-- ----------------------------------------------------------------

architecture basic of lfsr4 is
-- Internal LFSR register
signal data : bit_vector(3 downto 0);

begin

-- LFSR shift-register
p1: process(clk, rstN)
begin
if (rstN = '0') then
q <= (others => '1');
elsif rising_edge(clk) then
if (load = '1') then
q <= seed1;
elsif (enable = '1') then
q <= (q(1) xor q(0)) & q(3 downto 1);
end if;
end if;
end process p1;

-- Output
data <= q;

end architecture;


RXR CODE:

library ieee;
use ieee.std_logic_1164.all;

-- ----------------------------------------------------------------

entity rxr4 is
port (
rstN : in std_logic;
clk : in std_logic;

-- Load the LFSR register
q : in bit_vector(3 downto 0);

-- LFSR register (1-bit of this is the PRBS signal)
led : out bit_vector(3 downto 0)

);
end entity;

-- ----------------------------------------------------------------

architecture basic of rxr4 is
-- Internal LFSR register
signal p,data2 : bit_vector(3 downto 0);
signal m,error,n : integer := 0 ;

begin


p2rocess(clk,q)
begin

--if (rstN = '0') then
-- p <= (others => '1');
--elsif rising_edge(clk) then
--if (load = '1') then
--p <= seed2;
-- else



if rising_edge(clk) then
n<=n+1;
if n=0 and q= "0001" then
p <= q ;
elsif n=0 then

p<= "0001";
--elsif (enable = '1') then
else
p <= ( p(1) xor p(0)) & p(3 downto 1);
end if;
end if;

end process p2;

--displaying count value using LEDs



data2 <= p;

-- checking for error

p3: process (p)
begin

-- to display error using LEDs after 15 bits are checked
if m>0 then

if m=16 then

case error is
when 0 => led <= "0000";
when 1 => led <= "0001";
when 2 => led <= "0010";
when 3 => led <= "0011";
when 4 => led <= "0100";
when 5 => led <= "0101";
when 6 => led <= "0110";
when 7 => led <= "0111";
when 8 => led <= "1000";
when 9 => led <= "1001";
when 10 => led <= "1010";
when 11 => led <= "1011";
when 12 => led <= "1100";
when 13 => led <= "1101";
when 14 => led <= "1110";
when 15 => led <= "1111";
when others => led <= "0000";
end case;
end if;



if (p(0)/= q(0)) then
error <= error + 1 ;

end if;

end if;
m<=m+1;

end process p3;

end architecture;
 

Re: error while using for generate


Hmmm, I saw some syntax tags in the stuff I cut out...just not around the code. You need to add the following before your code (syntax=vhdl) but use [] instead of () and add (/syntax) after your code. There is a banner above this forum: "Announcement: Use CODE or SYNTAX tags for code posted in messages" from alexan_e that describes using tags.

Let me see if I understand. You are trying to perform an lfsr operation generating 4-bits and send those bits to your Txr. What you are trying to do should not be done in a loop. Loops in VHDL are unraveled they do not behave like software loops. So look at my example code, which shows all the instances are in parallel and connected to the same set of inputs and outputs.

You need to add an FSM to cycle through the number of iterations you want to compute. So instead the FSM would control when the lfsr produces data for the Txr and then subsequently determines when the output led data is ready to send out.

Note: I see why you used inout for the q port, You need to use an internal signal for q like q_internal and then assign it to the output port q <= q_internal;. Then you can change q to an out.

regards.
 
Last edited:

Re: error while using for generate

rashmi.imhsar;1338862 said:
How do I attach my code ?I could not find syntax tags icon anywhere !
Click to expand...
See this for an explanation how to:
 

Re: error while using for generate

Thanks. Will find out about FSM.

Will this code do the work I wanted to ?
When simulated in model sim, it gave proper values.

Instead of using components, I tried this:


Code VHDL - [expand]
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-- A 4-bit Linear feedback shift-register (LFSR)-PRBS & BERT.
--
-- ----------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
-- ----------------------------------------------------------------
 
entity lfsr4_txrrxr is
    port (
    rstN   : in  std_logic;
        clk    : in  std_logic;
 
        -- Load the LFSR register
        load   : in  std_logic;
        
        
        -- transmitter LFSR seed value (eg, 0001)
        seed1   : in  bit_vector(3 downto 0);
        
        -- receiver LFSR seed value (seed1 & seed2 are different to check for error) (eg, 1001)
        --seed2   : in  bit_vector(3 downto 0);
 
        -- Enable the LFSR register
        enable : in  std_logic;
        data : out bit_vector(3 downto 0);
 
        -- LFSR register (1-bit of this is the PRBS signal)
        led   : out bit_vector(3 downto 0)
        
        
    );
end entity;
 
-- ----------------------------------------------------------------
 
architecture basic of lfsr4_txrrxr is
    -- Internal LFSR register
    signal q : bit_vector(3 downto 0);
    signal p : bit_vector(3 downto 0);
    signal error,m,n:integer:=0;
begin
 
    -- LFSR shift-register
p1: process(clk, rstN)
    begin
        if (rstN = '0') then
            q <= (others => '1');
        elsif rising_edge(clk) then
            if (load = '1') then
                q <= seed1;
            elsif (enable = '1') then
                q <= (q(1) xor q(0)) & q(3 downto 1);
            end if;
        end if;
    end process p1;
 
    -- Output
    data <= q;
    
    -- Receiver
    
 
p2:process(clk,q)
    begin
     
    if rising_edge(clk) then  
     n<=n+1;
                   if n=0 and q= "0001" then
                   p <= q ;
               elsif n=0 then
                 p <= "0001";
               else
                  p <= ( p(1) xor p(0)) & p(3 downto 1);
               end if;           
        end if;
            
end process p2; 
                  
    
  -- checking for error
     
p3: process (p)         
begin   
 
  -- to display error using LEDs after 15 bits are checked
  
  
 if m=16 then
  
    
  case error is
  when 0 => led <= "0000";
  when 1 => led <= "0001";
  when 2 => led <= "0010";
  when 3 => led <= "0011";
  when 4 => led <= "0100";
  when 5 => led <= "0101";
  when 6 => led <= "0110";
  when 7 => led <= "0111";
  when 8 => led <= "1000";
  when 9 => led <= "1001";
  when 10 => led <= "1010";
  when 11 => led <= "1011";
  when 12 => led <= "1100";
  when 13 => led <= "1101";
  when 14 => led <= "1110";
  when 15 => led <= "1111";
  when others => led <= "0000";
  end case;
  end if;
       
       
        
             if (p(0)/= q(0)) then
       error <= error + 1;
       
       end if;
       m<=m+1;
       
end process p3;      
 
end architecture;
 

Re: error while using for generate

Process p3 needs to be a clocked process if you plan on incrementing error and m. Besides that the p3 process is missing signals in the sensitivity list. Also as m is is incremented and is never reset once m reaches 16 it will keep getting incremented until it eventually rolls over. Is that really the behavior you wanted. The p3 process looks like it was never designed.

Regards
 

Re: error while using for generate

When I simulated in model sim, the m and error values got incremented even without clk in the p3 sensitivity list. Clk is needed ?

Will this code work as a transmitter and error tester when loaded in a fpga?
 

They will have updated whenever P changed, but this will not match the real hardware (real hardware ignores sensitivity list). SO no, it will not match the simulation behaviour on real hardware.
 

Do you understand this code represents hardware and not a software program? So whatever code you write for an FPGA will need to be converted to sequential and combinational logic.

It's not a mater of is Clk needed, it's the fact that you need to have registers inferred to store the last value of m and the last value of error so you can increment them and make the result a new value that gets loaded into m and error. As Tricky mentions your simulation won't match the hardware that is generated...what you'll likely end up with latches (which are strongly discouraged to have in a design) in the design as they will require special constraints to deal with in the static timing analysis.

From what I saw the addition of a register to m, error, and perhaps even led won't affect the error detection but it will result in hardware that matches the simulation results.
 

oh ok . I have included clk in the code and its working fine in simulation.

Will this work in the hardware too like how I wanted it to work?


Code VHDL - [expand]
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library ieee;
use ieee.std_logic_1164.all;
 
-- ----------------------------------------------------------------
 
entity lfsr4_txrrxr is
    port (
    rstN   : in  std_logic;
        clk    : in  std_logic;
 
        -- Load the LFSR register
        load   : in  std_logic;
        
        -- transmitter LFSR seed value (eg, 0001)
        seed1   : in  bit_vector(3 downto 0);
        
        -- Enable the LFSR register
        enable : in  std_logic;
        data : out bit_vector(3 downto 0);
 
        -- LFSR register (1-bit of this is the PRBS signal)
        led   : out bit_vector(3 downto 0)
            
    );
end entity;
 
-- ----------------------------------------------------------------
 
architecture basic of lfsr4_txrrxr is
    -- Internal LFSR register
    signal q : bit_vector(3 downto 0);
    signal p : bit_vector(3 downto 0);
    signal error,m,n:integer:=0;
    signal r,k: integer:= 0;
begin
 
    -- LFSR shift-register
    
p1: process(clk, rstN)
    begin
        if (rstN = '0') then
            q <= (others => '1');
        elsif rising_edge(clk) then
            if (load = '1') then
                q <= seed1;
            elsif (enable = '1') then
                q <= (q(1) xor q(0)) & q(3 downto 1);
            end if;
        end if;
    end process p1;
 
    -- Output
    data <= q;
    
    
    -- Receiver
    
p2:process(clk,q)
    begin
     
    if rising_edge(clk) then 
     --k<=k-1; 
     n<=n+1;
                 if n=0 and q= "0001" then
                   p <= q ;
               elsif n=0 then
                 p <= "0001";
               else
                  p <= ( p(1) xor p(0)) & p(3 downto 1);
               end if;      
               r<=2; 
        end if;
            
end process p2; 
                  
    
  -- checking for error
     
p3: process (clk,p)         
begin   
 
  -- to display error using LEDs after 15 bits are checked
k<=r;  
if k=2 then   
  
 if m=16 then
     
 case error is
  when 0 => led <= "0000";
  when 1 => led <= "0001";
  when 2 => led <= "0010";
  when 3 => led <= "0011";
  when 4 => led <= "0100";
  when 5 => led <= "0101";
  when 6 => led <= "0110";
  when 7 => led <= "0111";
  when 8 => led <= "1000";
  when 9 => led <= "1001";
  when 10 => led <= "1010";
  when 11 => led <= "1011";
  when 12 => led <= "1100";
  when 13 => led <= "1101";
  when 14 => led <= "1110";
  when 15 => led <= "1111";
  when others => led <= "0000";
  end case;
  end if;
       
       
             if (p(0)/= q(0)) then
       error <= error + 1;
       
       end if;
       m<=m+1;
       k<=0;
       end if;
       
end process p3;
     
 
end architecture;
 

Get rid of the p and q in the sensitivity lists:
Code: 
p2:process(clk,q)
p3: process (clk,p)

should be just
Code: 
p2:process(clk)
p3: process (clk)

and add a proper clock structure in p3 as that process is still a combinational process as clk is never used:

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p3; process (clk)
begin
  if rising_edge (clk) then
  --...
  --insert your code
  --...
  end if;
end process p3;
 

I have made all the changes. This code works in simulation. Any other chnages I have to make to make it work in hardware?


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library ieee;
use ieee.std_logic_1164.all;
 
-- ----------------------------------------------------------------
 
entity lfsr4_txrrxr is
    port (
    rstN   : in  std_logic;
        clk    : in  std_logic;
 
        -- Load the LFSR register
        load   : in  std_logic;
        
        -- transmitter LFSR seed value (eg, 0001)
        seed1   : in  bit_vector(3 downto 0);
        
        -- Enable the LFSR register
        enable : in  std_logic;
        data : out bit_vector(3 downto 0);
 
        -- LFSR register (1-bit of this is the PRBS signal)
        led   : out bit_vector(3 downto 0)
            
    );
end entity;
 
-- ----------------------------------------------------------------
 
architecture basic of lfsr4_txrrxr is
    -- Internal LFSR register
    signal q : bit_vector(3 downto 0);
    signal p : bit_vector(3 downto 0);
    signal error,m,n:integer:=0;
    signal r,k,c,a: integer:= 0;
begin
 
    -- LFSR shift-register
    
p1: process(clk, rstN)
    begin
     -- c<=0;
        if (rstN = '0') then
            q <= (others => '1');
        elsif rising_edge(clk) then
              if (load = '1') then
                 q <= seed1;
              elsif (enable = '1') then
                 q <= (q(1) xor q(0)) & q(3 downto 1);
              end if;
        --c<=2;
        end if;
        
    end process p1;
 
    -- Output
    data <= q;
    
    
    -- Receiver
    
p2:process(clk)
    begin
     
    if rising_edge(clk) then 
     --a<=c;
     --if a=2 then
      
     n<=n+1;
                 if n=0 and q= "0001" then
                   p <= q ;
               elsif n=0 then
                 p <= "0001";
               else
                  p <= ( p(1) xor p(0)) & p(3 downto 1);
               end if;      
               r<=2;
                    --a<=0; 
               end if;
 
        --end if;
            
end process p2; 
                  
    
  -- checking for error
     
p3: process (clk)           
begin   
 
if rising_edge(clk) then  
  -- to display error using LEDs after 15 bits are checked
k<=r;  
if k=2 then   
  
 if m=16 then
     
 case error is
  when 0 => led <= "0000";
  when 1 => led <= "0001";
  when 2 => led <= "0010";
  when 3 => led <= "0011";
  when 4 => led <= "0100";
  when 5 => led <= "0101";
  when 6 => led <= "0110";
  when 7 => led <= "0111";
  when 8 => led <= "1000";
  when 9 => led <= "1001";
  when 10 => led <= "1010";
  when 11 => led <= "1011";
  when 12 => led <= "1100";
  when 13 => led <= "1101";
  when 14 => led <= "1110";
  when 15 => led <= "1111";
  when others => led <= "0000";
  end case;
  end if;
       
       
             if (p(0)/= q(0)) then
       error <= error + 1;
       
       end if;
       m<=m+1;
       k<=0;
       end if;
       end if;
end process p3;
     
 
end architecture;
 

You need to use better signal names. Single character signal names are frowned upon by most engineers that have to maintain something later. I guarantee it will take you quite a while to understand what you were doing in this code just 1 month from now, given the lack of comments and signal names like k, r, m, a, c, etc.

What is r for? It only gets assigned to a value of 2 and then later k gets assigned that value. After that k toggles between the value of 2 and 0. Is r supposed to be a flag to only allow compares at a certain time? If so there are easier ways to code this.

Based on what I've seen so far and the changes you've been making. I get the feeling that you don't have a circuit design in your head and are sort of designing this code in a text editor. You need to understand what you are designing using block diagrams and timing diagrams of the circuit. Once you've worked out how the design is supposed to function then you can start writing code.

Regards
 

Yes I can understand.

I want to use a single FPGA to act as a PRBS generator and as a BERT. The data is to be passed through optic fibre medium.

Txr PRBS generator(FPGA)-->DAC-->SMA Connector-->electrical amplifier-->fiber-->electrical amp-->ADC-->Rxr(FPGA).

Code VHDL - [expand]
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library ieee;
use ieee.std_logic_1164.all;
 
-- ----------------------------------------------------------------
 
entity lfsr4_txrrxr is
    port (
    rstN     : in  std_logic;
        clk      : in  std_logic;
 
        -- Load the LFSR register
        load     : in  std_logic;
        
 
        -- Enable the LFSR register
        enable   : in  std_logic;
        data    : out bit_vector(3 downto 0);
 
        -- To display the Error value using LEDs
        led      : out bit_vector(3 downto 0);
        
        rxd_data : in bit_vector( 3 downto 0)
            
    );
end entity;
 
-- ----------------------------------------------------------------
 
architecture basic of lfsr4_txrrxr is
    -- Internal LFSR register
    signal txd: bit_vector(3 downto 0);
    signal rxr_lfsr : bit_vector(3 downto 0);
    signal error,bits_tested,n,w:integer:=0;
    signal flag,flag_copy: integer:= 0;
begin
 
    -- LFSR shift-register
    
p1: process(clk, rstN)
    begin
     
    if (rstN = '1') then        
        if rising_edge(clk) then
          w<=w+1;
              if (load = '1' and w=0) then
                 txd <= "0001";
              elsif (w/= 0) then
                 txd <= (txd(1) xor txd(0)) & txd(3 downto 1);
              end if;
        
        end if;
        end if;
        
    end process p1;
 
    -- Output data --> DAC input pins
    
    data <= txd;
    
    
    
    -- data --> assigned to DAC pins
    -- DAC is enabled already
    -- analog output from DAC --> SMA connector --> input to ADC 
    -- ADC output pins --> rxd_data
 
 
    
    -- Receiver
    
p2:process(clk)
    begin
    
    if (rstN = '1') then 
     if rising_edge(clk) then 
       if (rxd_data /= "0000") then
              
     n<=n+1;
                 if n=0 then
                    rxr_lfsr <= "0001";
               else
                    rxr_lfsr <= (rxr_lfsr(1) xor rxr_lfsr(0)) & rxr_lfsr(3 downto 1);
               end if;      
               
               flag<=2;
                
              end if;
     end if;
  end if;
end process p2; 
                  
    
  -- checking for error
     
p3: process (clk)           
begin   
 
if rising_edge(clk) then  
 
  -- to display error using LEDs after 15 bits are checked
flag_copy<=flag;  
 
if flag_copy=2 then   
  
 if bits_tested=16 then
     
 case error is
  when 0 => led <= "0101";
  when 1 => led <= "0001";
  when 2 => led <= "0010";
  when 3 => led <= "0011";
  when 4 => led <= "0100";
  when 5 => led <= "0101";
  when 6 => led <= "0110";
  when 7 => led <= "0111";
  when 8 => led <= "1000";
  when 9 => led <= "1001";
  when 10 => led <= "1010";
  when 11 => led <= "1011";
  when 12 => led <= "1100";
  when 13 => led <= "1101";
  when 14 => led <= "1110";
  when 15 => led <= "1111";
  when others => led <= "1111";
  end case;
  end if;
       
       
             if (rxr_lfsr(0)/= rxd_data(0)) then
       error <= error + 1;
       
       end if;
       bits_tested<=bits_tested+1;
       flag_copy<=0;
       end if;
       end if;
end process p3;
     
 
end architecture;



I want the Rxr LFSR value and the rxd_data value to be compared only after data from the txd has been received by rxd_data.

data --> DAC input pins
rxd_data --> ADC output pins

Also,how do I make sure that the received data in rxd_data is the one that was transmitted or if it some junk value? I could not understand how a suffix could be added to the data sequence to check for this.
 


Yes, I get you understand the system that you are trying to implement. What you haven't seem to have done is the actual implementation design, i.e. registers and the logic that is required between those registers.

Code VHDL - [expand]
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p1: process(clk, rstN)
    begin
     
    if (rstN = '1') then        
        if rising_edge(clk) then
          w<=w+1;
              if (load = '1' and w=0) then
                 txd <= "0001";
              elsif (w/= 0) then
                 txd <= (txd(1) xor txd(0)) & txd(3 downto 1);
              end if;
        end if;
    end if;
        
    end process p1;

Like this, what you really want is a leading edge detection of load. Using a counter to detect when load goes high for the first time isn't a good way to handle this, especially as there is no way to reset w back to 0 without reprogramming the FPGA or waiting for w to rollover. This is what I mean't by designing in a text editor. You're just adding stuff to make the simulation work and aren't actually designing a circuit to do the job.


You'll have to design a synchronization circuit to align the rxd_data with the rxr_lfsr.
A couple of options come immediately to mind:
1) have a rxr_lfsr compare register with some number of nibbles you've sent and perform a compare against the rxd_data until you have a match then you can start shifting through the rxr_lfsr compare data you're generating in the BERT and compare it with the incoming rxd_data that you've synchronized with the rxr_lfsr.
2) load (initialize) the rxr_lfsr with data from the rxd_data, once initialized start comparing, if it doesn't compare properly then there was an error in the bits that you initialized with, so start another load and try again. You could keep track of the number of retires to synchronize and stop trying if it goes over a certain number of times.

Regards
 

The BERT counts the number of erroneous bits in the received data. If we try to match the rxd_data with the rxr_lfsr value to synchronize the two values, it means we are assuming that the first data rxd will not have error right?

Say I am using seed value as "0001" at the Txr. So I am using the same seed value for the Rxr LFSR also. From what I understood, you are saying that the Rxr LFSR value should be compared with the Rxd value and untill both are equal the process should continue?

My doubt is, if the channel had produced erroneous bit during the first iteration itself, then the error will be missed .

- - - Updated - - -

In the second point: The rxr_lfsr is to be initialised with the rxd_data (the seed used at the txr lfsr) and the rxr_lfsr is compared with the rxd_data?

If the channel had changed the actual seed value used in the txr, the new erroneous value will be the seed to the rxr_lfsr right? then the subsequent values when compared will produce error always. This is what is confusing me
 

In any system where BERT is used, you will have errors at startup, unless there is some other signal or embedded coding that designates a start of data (some sort of framing signal). As you only have a receive input that is transmitting "raw" lfsr data you have no capability of any kind of framing.

My doubt is, if the channel had produced erroneous bit during the first iteration itself, then the error will be missed .
Click to expand...
Yes you will likely have missed the erroneous bit in the first seed value of "0001", but that is inherent in the way the interface is designed with raw lfsr data. If you want to know where data starts/stops etc. then use some coding scheme like 8b10 and then you can use specific K-codes to define the start and stopping point of the data. Then your FSM only needs to monitor the stream for the correct start K-code and begin comparing from the next bits on.

Yes, it will error continuously, hence additional logic is required to detect that error and restart synchronization of the BERT with the rxd_data. If the channel is too noisy then it will likely never synchronize properly. If that is the case then channel should have error correction encoding added.

Regards
 

Ok. I will look into that.

I kind of understood what can be done but still have a doubt in that.

Say am using a seed value of "0001" at the Txr lfsr. And say the value is received as "1001" at the Rxr due to channel distortions. This value (1001) is given as seed to the Rxr lfsr.

This seed value of the Rxr lfsr is compared with the incoming value from the Txr untill it matches with 1001. Once it matches, the Rxr lfsr will start generating the sequence and the next received data is compared with the next four bits generated by the Rxr lfsr and error counting should begin.

But my doubt is, the rxd data which matched with the Rxr lfsr seed value "1001" could have actually been transmitted as , say, "1000" at the txr.
In this case, once the Rxr lfsr is activated after matching, it will be comparing "1100"(rxr lfsr gen value following seed value of 1001) with "0100"(the actual value generated by the txr lfsr following the value 1000).

So I do not understand how this synchronization can be done using this kind of method.
 

You should reread post #16. I made two different suggestions to synchronize.
1) seed the BIST lfsr to compare against the received data using the first received data. From that point on you will be generating BIST lfsr data and comparing it against the incoming received data. If you have continuous mismatches the first seed value was bad.

2) load the BIST lfsr and wait to enable generating new BIST lfsr data until the BIST lfsr and the received data match. If the receive data was bad and ended up matching then the data won't be synchronized and you'll have continuous mismatches. So you will need to disable the BIST lfsr and restart comparing the BIST lfsr with in the receive data.

Both methods rely on the first compare being correct otherwise the compares start off mismatched from the next compare on.

You have to keep repeatedly trying to synchronize every time the compares don't match continuously after you started. In a test platform I developed using a PRBS-23 sequence I used the seeding method as waiting for the PRBS-23 sequence to cycle could have taken 20 seconds or more with lowest data rate we needed to support. If the first seed value was incorrect the bit error count would increment continuously. If that condition was detected then the design would resync by reloading the PRBS-23 with a new seed from the received data.
 

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