Error while running simulation in the vhdl code using when else

[manishpatkar]

i was just practicing basics in vhdl with vivado. i wrote a simple when else staement , the synthesis worked perfectely but when i ran behavorial simulation i got following error

ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors

this is what i found in the Tcl console.

ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or 'C:/Users/manishpatkar/when_else/when_else.sim/sim_1/behav/xvhdl.log' file for more information.
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.


i checked the folder C:/Users/manishpatkar/when_else/when_else.sim/sim_1/behav/xvhdl.log and it had

INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/manishpatkar/when_else/when_else.srcs/sources_1/new/when_else.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity when_else
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/manishpatkar/when_else/when_else.srcs/sim_1/new/when_else_tb.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity when_else_tb
ERROR: [VRFC 10-1412] syntax error near - [C:/Users/manishpatkar/when_else/when_else.srcs/sim_1/new/when_else_tb.vhd:46]
ERROR: [VRFC 10-1504] unit bench ignored due to previous errors [C:/Users/manishpatkar/when_else/when_else.srcs/sim_1/new/when_else_tb.vhd:8]
INFO: [VRFC 10-240] VHDL file C:/Users/manishpatkar/when_else/when_else.srcs/sim_1/new/when_else_tb.vhd ignored due to errors



here is the code

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date: 10/26/2017 11:37:53 AM
-- Design Name: 
-- Module Name: when_else - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity when_else is
 Port (
        A , B , C : in std_logic;
       Assign_1 , Assign_2 : in std_logic;
       Z : out std_logic  );
end when_else;

architecture Behavioral of when_else is

begin

Z <= A when Assign_1 = '1' else
     B when Assign_2 = '1' else
     C;

end Behavioral;

------------------------------------------------------------------------------------------
and the test bench is

library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_Std.all;

entity when_else_tb is
end;

architecture bench of when_else_tb is

  component when_else
   Port (
          A , B , C : in std_logic;
         Assign_1 , Assign_2 : in std_logic;
         Z : out std_logic  );
  end component;

  signal A , B , C: std_logic;
  signal Assign_1 , Assign_2: std_logic;
  signal Z: std_logic ;

begin

  uut: when_else port map ( A        => A,
                            B        => B,
                            C        => C,
                            Assign_1 => Assign_1,
                            Assign_2 => Assign_2,
                            Z        => Z );

  stimulus: process
  begin
  
    -- Put initialisation code here
     A <= '1';
     B <= '0';
     C <= '1';
     Assign_1 <='0';
     Assign_1 <='1';
     
     wait for 10 ns;
     Assign_1 <='1';
     Assign_2 <='0';
     
     wait for 10 ns;
     Assign_1 <='0';
     Assign-2 <='0';

    -- Put test bench stimulus code here

    wait;
  end process;

end;


-------------------------------------------------------------

I am trying but not able to find what caused did! someone please help!

 

[FvM]

Re: error while running simulation in the vhdl code using when else

You absolutely need to learn how to read error messages!

ERROR: [VRFC 10-1412] syntax error near -
[C:/Users/manishpatkar/when_else/when_else.srcs/sim_1/new/when_else_tb.vhd:46]

The verbose log is indicating a single syntax error with a source line number. Just locate the line and find out what's wrong here.

The problem turns out as trivial typo.

Assign[COLOR="#FF0000"]-[/COLOR]2 <='0';