vivek20055
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THERMAL RELIEF ERRORS REPORT -- Ind_Hea 3.pcb -- Tue Jan 29 09:21:04 2013
Drilled pads with Nondrilled pads with
less than 50% thermal extensions less than 50% thermal extensions
Report of Thermal Spokes Generator.
On GND Layer:
(60.35, 28.45) # = 0
(20.27, 32.26) # = 0
(19.4, 28.76) # = 0
(28.04, 30.69) # = 0
(26.95, 26.41) # = 0
(24.93, 24.82) # = 0
(23.51, 25.9) # = 0
(56.41, 29.04) # = 0
Total Drilled pads: 8 Total Nondrilled pads: 0
Hi vivek,
For your input i understand why your professor prefer 4 layer ,the following things you need to consider,
1.no of components and no of nets need to consider.(see in your design has USB,QFN ,MOSFET ) for routing.in USB it is need at least 2 layer like that each component need to consider
2.depends on board size layer count may be vary .(if board size is big we can try it in 2 layer).
3.mostly no of nets (power,critical nets,clock net) as well as board size impact the layer count .in case in your design has more amount of power nets is there so that only they prefer 4layer
4.depends on application. this also important role for choosing 4 layer
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