CG: loading common design graph ...
INFO: using TLU capacitance model
ERROR : no TLU cap table exists in the library
Error in creating TLU models
CG: Release 0 cache blocks
ERROR : Fail to get delay/trans thresholds
writeSDF failed
Fail to execute command
Astro support TLU and TLU plus module for parastic estimation. which are chose in Timing Setup Sheet.
usually, the TLU model exist in the Technology File, with the format of capacitance lookup table.
while the TLUplus model is generate form the .nxgrd format, which is for RCXtract stage. and you have to check the RCXtraction Reference manual for TLU plus model generation.
I generate TLU module based on your help. Thanks a lot!
But problem still exists when trying SDF Out:
LEQ: updating cell master classes ...
LEQ: Reading footprint equivalent classes.
CG: Extracting pin LEQ.
LEQ: completed. (runtime = 0 sec)
CG: Default voltage area DEFAULT_VA created
ERROR : No clock definition. Please add clock or virtual clock definition.
VR: Virtual Routing Completed
ERROR : Fail to get delay/trans thresholds
writeSDF failed
Fail to execute command
I tried to specify Clock Net in "Clock Common Options" dialog but the above problem couldn't be solved.
Anyone can help me futher?
Thanks a lot!
Added after 3 hours 56 minutes:
I solve this problem by myself:
first generate SDC file after synthesis (write_sdc in dc-compiler)
then load SDC file after placement in Astro, specifiy clock net name
you can run CTS now.