Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Error when loading the testbench in Modelsim

Status
Not open for further replies.

samuel_john

Member level 1
Member level 1
Joined
Nov 21, 2003
Messages
37
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
385
modelsim report

Loading D:/modelsim5.7f/win32/../std.standard
# Loading D:/modelsim5.7f/win32/../ieee.std_logic_1164(body)
# Loading D:/modelsim5.7f/win32/../ieee.numeric_std(body)
# Loading D:/modelsim5.7f/win32/../ieee.std_logic_arith(body)
# Loading D:/modelsim5.7f/win32/../ieee.std_logic_unsigned(body)
# Loading work.testbench(behavior)
Loading work.processor_interface(beh)
# ** Fatal: (SIGSEGV) Bad pointer access.
# Time: 0 ns Iteration: 0 Process: /testbench/tb File: E:/altera/xilinx/e1_config20nov/tst_processor_interface.vhd
# FATAL ERROR while loading design

have anyone encounter such a problem in modelsim...this happens when loading the testbench....while loading an entity alone there is no problem.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top