Error when loading the testbench in Modelsim

[samuel_john]

modelsim report

Loading D:/modelsim5.7f/win32/../std.standard
# Loading D:/modelsim5.7f/win32/../ieee.std_logic_1164(body)
# Loading D:/modelsim5.7f/win32/../ieee.numeric_std(body)
# Loading D:/modelsim5.7f/win32/../ieee.std_logic_arith(body)
# Loading D:/modelsim5.7f/win32/../ieee.std_logic_unsigned(body)
# Loading work.testbench(behavior)
Loading work.processor_interface(beh)
# ** Fatal: (SIGSEGV) Bad pointer access.
# Time: 0 ns Iteration: 0 Process: /testbench/tb File: E:/altera/xilinx/e1_config20nov/tst_processor_interface.vhd
# FATAL ERROR while loading design

have anyone encounter such a problem in modelsim...this happens when loading the testbench....while loading an entity alone there is no problem.