Error voltage in a flyback smps circuit design

[tempora123]

Hello,

I have this flyback smps circuit:


when simulating the behaviour I get the following output:


My question is if the behaviour of the error voltage (at the "+" input of U1) is correct?
The error amp has an open loop for DC in this configuration, is it ok?

Thank you for your answers.
BR.

 

[Prototyp_V1.0]

Re: flyback design issue

That behaviour is because the feedback stage only consist of a opamp integrator. Reducing R3 will reduce the time of the spike.

An integrator's output voltage will increase over time, depending on relationship between R3 ant opamps feedback capasitors. That also means that ERROR SIGNAL TAKES TIME to get to it's "stable" level.
It isn't really not stable, but it slightly move voltage up and down in an effort to keep output voltage stable.

Another backdraw using only integrator is that a sudden change in load can cause a voltage spike on output. A little one, but still. A derivator (in addition to the integrator) will take care of that.

To resolve that problem, you should have combined a integrator (as you already have), derivator and a regular inverted opamp stage. Look for PID control on the net.

 

[tempora123]

Re: flyback design issue

Thanks for the reply. I will take a look at the PID control as you suggest. But in case the loop is open for DC I still get it to lock. That is what has driven my curiosity.