[SOLVED] error undefined symbol RC

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shari2643

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Hi ppl, i am trying to set
HTML: 
external oscillator RC
but it is continuously giving the error
HTML: 
Undefined symbol
. i referred to htc.h and pic18f4520.h but config settings are not there.I also read blogs and datasheets still yet no progress . Could anyone plz guide me thankx

Compiler:hitech PICC18 PRO 9.63


Code: 
#include<htc.h>
#define _XTAL_FREQ 20000000 // 20Mhz crystal for delay in ms

 //__CONFIG(1, FOSC_EXTRC  & FCMDIS & IESODIS);  undefined FOSC_EXTRC
 //__CONFIG(1, RC  & FCMDIS & IESODIS);   undefined RC           // 1H

 __CONFIG(1, XT  & FCMDIS & IESODIS);              //WORKS PERFECTLY 
 __CONFIG(2,  WDTDIS & PWRTEN & BORDIS ); // 2H 2L
 

18F4520 Support Information

#pragma config Usage

#pragma config <setting>=<named value>

For example:
// Internal/External Oscillator Switchover bit: Oscillator Switchover mode disabled
// Oscillator Selection bits: External RC oscillator, port function on RA6
// Fail-Safe Clock Monitor Enable bit: Fail-Safe Clock Monitor disabled
#pragma config IESO = OFF, OSC = RCIO6, FCMEN = OFF
#pragma config <setting>=<literal constant>

For example:
// Internal/External Oscillator Switchover bit: Oscillator Switchover mode disabled
// Oscillator Selection bits: External RC oscillator, port function on RA6
// Fail-Safe Clock Monitor Enable bit: Fail-Safe Clock Monitor disabled
#pragma config IESO = 0x0, OSC = 0x7, FCMEN = 0x0
#pragma config <register>=<literal constant>

For example:
// Internal/External Oscillator Switchover bit: Oscillator Switchover mode disabled
// Oscillator Selection bits: External RC oscillator, port function on RA6
// Fail-Safe Clock Monitor Enable bit: Fail-Safe Clock Monitor disabled
#pragma config CONFIG1H = 0x7

For example:
// IDLOC @ 0x200000
#pragma config IDLOC0 = 0xFF
#pragma config Settings

Register: CONFIG1H @ 0x300001

IESO = Internal/External Oscillator Switchover bit
OFF Oscillator Switchover mode disabled
ON Oscillator Switchover mode enabled
OSC = Oscillator Selection bits
RCIO6 External RC oscillator, port function on RA6
RC External RC oscillator, CLKO function on RA6
INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7
XT XT oscillator
LP LP oscillator
HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1)
ECIO6 EC oscillator, port function on RA6
EC EC oscillator, CLKO function on RA6
INTIO67 Internal oscillator block, port function on RA6 and RA7
HS HS oscillator
FCMEN = Fail-Safe Clock Monitor Enable bit
OFF Fail-Safe Clock Monitor disabled
ON Fail-Safe Clock Monitor enabled
Register: CONFIG2L @ 0x300002

BOREN = Brown-out Reset Enable bits
NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled)
OFF Brown-out Reset disabled in hardware and software
ON Brown-out Reset enabled and controlled by software (SBOREN is enabled)
SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled)
BORV = Brown Out Reset Voltage bits
1
2
3 Minimum setting
0 Maximum setting
PWRT = Power-up Timer Enable bit
OFF PWRT disabled
ON PWRT enabled
Register: CONFIG2H @ 0x300003

WDTPS = Watchdog Timer Postscale Select bits
8 1:8
1 1:1
32768 1:32768
1024 1:1024
2 1:2
32 1:32
16 1:16
16384 1:16384
128 1:128
4096 1:4096
64 1:64
8192 1:8192
2048 1:2048
512 1:512
256 1:256
4 1:4
WDT = Watchdog Timer Enable bit
OFF WDT disabled (control is placed on the SWDTEN bit)
ON WDT enabled
Register: CONFIG3H @ 0x300005

CCP2MX = CCP2 MUX bit
PORTC CCP2 input/output is multiplexed with RC1
PORTBE CCP2 input/output is multiplexed with RB3
PBADEN = PORTB A/D Enable bit
OFF PORTB<4:0> pins are configured as digital I/O on Reset
ON PORTB<4:0> pins are configured as analog input channels on Reset
LPT1OSC = Low-Power Timer1 Oscillator Enable bit
OFF Timer1 configured for higher power operation
ON Timer1 configured for low-power operation
MCLRE = MCLR Pin Enable bit
OFF RE3 input pin enabled; MCLR disabled
ON MCLR pin enabled; RE3 input pin disabled
Register: CONFIG4L @ 0x300006

DEBUG = Background Debugger Enable bit
OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins
ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
STVREN = Stack Full/Underflow Reset Enable bit
OFF Stack full/underflow will not cause Reset
ON Stack full/underflow will cause Reset
XINST = Extended Instruction Set Enable bit
OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
ON Instruction set extension and Indexed Addressing mode enabled
LVP = Single-Supply ICSP Enable bit
OFF Single-Supply ICSP disabled
ON Single-Supply ICSP enabled
Register: CONFIG5L @ 0x300008

CP0 = Code Protection bit
OFF Block 0 (000800-001FFFh) not code-protected
ON Block 0 (000800-001FFFh) code-protected
CP1 = Code Protection bit
OFF Block 1 (002000-003FFFh) not code-protected
ON Block 1 (002000-003FFFh) code-protected
CP2 = Code Protection bit
OFF Block 2 (004000-005FFFh) not code-protected
ON Block 2 (004000-005FFFh) code-protected
CP3 = Code Protection bit
OFF Block 3 (006000-007FFFh) not code-protected
ON Block 3 (006000-007FFFh) code-protected
Register: CONFIG5H @ 0x300009

CPD = Data EEPROM Code Protection bit
OFF Data EEPROM not code-protected
ON Data EEPROM code-protected
CPB = Boot Block Code Protection bit
OFF Boot block (000000-0007FFh) not code-protected
ON Boot block (000000-0007FFh) code-protected
Register: CONFIG6L @ 0x30000A

WRT0 = Write Protection bit
OFF Block 0 (000800-001FFFh) not write-protected
ON Block 0 (000800-001FFFh) write-protected
WRT1 = Write Protection bit
OFF Block 1 (002000-003FFFh) not write-protected
ON Block 1 (002000-003FFFh) write-protected
WRT2 = Write Protection bit
OFF Block 2 (004000-005FFFh) not write-protected
ON Block 2 (004000-005FFFh) write-protected
WRT3 = Write Protection bit
OFF Block 3 (006000-007FFFh) not write-protected
ON Block 3 (006000-007FFFh) write-protected
Register: CONFIG6H @ 0x30000B

WRTB = Boot Block Write Protection bit
OFF Boot block (000000-0007FFh) not write-protected
ON Boot block (000000-0007FFh) write-protected
WRTC = Configuration Register Write Protection bit
OFF Configuration registers (300000-3000FFh) not write-protected
ON Configuration registers (300000-3000FFh) write-protected
WRTD = Data EEPROM Write Protection bit
OFF Data EEPROM not write-protected
ON Data EEPROM write-protected
Register: CONFIG7L @ 0x30000C

EBTR0 = Table Read Protection bit
OFF Block 0 (000800-001FFFh) not protected from table reads executed in other blocks
ON Block 0 (000800-001FFFh) protected from table reads executed in other blocks
EBTR1 = Table Read Protection bit
OFF Block 1 (002000-003FFFh) not protected from table reads executed in other blocks
ON Block 1 (002000-003FFFh) protected from table reads executed in other blocks
EBTR2 = Table Read Protection bit
OFF Block 2 (004000-005FFFh) not protected from table reads executed in other blocks
ON Block 2 (004000-005FFFh) protected from table reads executed in other blocks
EBTR3 = Table Read Protection bit
OFF Block 3 (006000-007FFFh) not protected from table reads executed in other blocks
ON Block 3 (006000-007FFFh) protected from table reads executed in other blocks
Register: CONFIG7H @ 0x30000D

EBTRB = Boot Block Table Read Protection bit
OFF Boot block (000000-0007FFh) not protected from table reads executed in other blocks
ON Boot block (000000-0007FFh) protected from table reads executed in other blocks
Register: IDLOC0 @ 0x200000

Register: IDLOC1 @ 0x200001

Register: IDLOC2 @ 0x200002

Register: IDLOC3 @ 0x200003

Register: IDLOC4 @ 0x200004

Register: IDLOC5 @ 0x200005

Register: IDLOC6 @ 0x200006

Register: IDLOC7 @ 0x200007

- - - Updated - - -

18F4520 Support Information

#pragma config Usage

#pragma config <setting>=<named value>

For example:
// Internal/External Oscillator Switchover bit: Oscillator Switchover mode disabled
// Oscillator Selection bits: External RC oscillator, port function on RA6
// Fail-Safe Clock Monitor Enable bit: Fail-Safe Clock Monitor disabled
#pragma config IESO = OFF, OSC = RCIO6, FCMEN = OFF
#pragma config <setting>=<literal constant>

For example:
// Internal/External Oscillator Switchover bit: Oscillator Switchover mode disabled
// Oscillator Selection bits: External RC oscillator, port function on RA6
// Fail-Safe Clock Monitor Enable bit: Fail-Safe Clock Monitor disabled
#pragma config IESO = 0x0, OSC = 0x7, FCMEN = 0x0
#pragma config <register>=<literal constant>

For example:
// Internal/External Oscillator Switchover bit: Oscillator Switchover mode disabled
// Oscillator Selection bits: External RC oscillator, port function on RA6
// Fail-Safe Clock Monitor Enable bit: Fail-Safe Clock Monitor disabled
#pragma config CONFIG1H = 0x7

For example:
// IDLOC @ 0x200000
#pragma config IDLOC0 = 0xFF
#pragma config Settings

Register: CONFIG1H @ 0x300001

IESO = Internal/External Oscillator Switchover bit
OFF Oscillator Switchover mode disabled
ON Oscillator Switchover mode enabled
OSC = Oscillator Selection bits
RCIO6 External RC oscillator, port function on RA6
RC External RC oscillator, CLKO function on RA6
INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7
XT XT oscillator
LP LP oscillator
HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1)
ECIO6 EC oscillator, port function on RA6
EC EC oscillator, CLKO function on RA6
INTIO67 Internal oscillator block, port function on RA6 and RA7
HS HS oscillator
FCMEN = Fail-Safe Clock Monitor Enable bit
OFF Fail-Safe Clock Monitor disabled
ON Fail-Safe Clock Monitor enabled
Register: CONFIG2L @ 0x300002

BOREN = Brown-out Reset Enable bits
NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled)
OFF Brown-out Reset disabled in hardware and software
ON Brown-out Reset enabled and controlled by software (SBOREN is enabled)
SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled)
BORV = Brown Out Reset Voltage bits
1
2
3 Minimum setting
0 Maximum setting
PWRT = Power-up Timer Enable bit
OFF PWRT disabled
ON PWRT enabled
Register: CONFIG2H @ 0x300003

WDTPS = Watchdog Timer Postscale Select bits
8 1:8
1 1:1
32768 1:32768
1024 1:1024
2 1:2
32 1:32
16 1:16
16384 1:16384
128 1:128
4096 1:4096
64 1:64
8192 1:8192
2048 1:2048
512 1:512
256 1:256
4 1:4
WDT = Watchdog Timer Enable bit
OFF WDT disabled (control is placed on the SWDTEN bit)
ON WDT enabled
Register: CONFIG3H @ 0x300005

CCP2MX = CCP2 MUX bit
PORTC CCP2 input/output is multiplexed with RC1
PORTBE CCP2 input/output is multiplexed with RB3
PBADEN = PORTB A/D Enable bit
OFF PORTB<4:0> pins are configured as digital I/O on Reset
ON PORTB<4:0> pins are configured as analog input channels on Reset
LPT1OSC = Low-Power Timer1 Oscillator Enable bit
OFF Timer1 configured for higher power operation
ON Timer1 configured for low-power operation
MCLRE = MCLR Pin Enable bit
OFF RE3 input pin enabled; MCLR disabled
ON MCLR pin enabled; RE3 input pin disabled
Register: CONFIG4L @ 0x300006

DEBUG = Background Debugger Enable bit
OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins
ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
STVREN = Stack Full/Underflow Reset Enable bit
OFF Stack full/underflow will not cause Reset
ON Stack full/underflow will cause Reset
XINST = Extended Instruction Set Enable bit
OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
ON Instruction set extension and Indexed Addressing mode enabled
LVP = Single-Supply ICSP Enable bit
OFF Single-Supply ICSP disabled
ON Single-Supply ICSP enabled
Register: CONFIG5L @ 0x300008

CP0 = Code Protection bit
OFF Block 0 (000800-001FFFh) not code-protected
ON Block 0 (000800-001FFFh) code-protected
CP1 = Code Protection bit
OFF Block 1 (002000-003FFFh) not code-protected
ON Block 1 (002000-003FFFh) code-protected
CP2 = Code Protection bit
OFF Block 2 (004000-005FFFh) not code-protected
ON Block 2 (004000-005FFFh) code-protected
CP3 = Code Protection bit
OFF Block 3 (006000-007FFFh) not code-protected
ON Block 3 (006000-007FFFh) code-protected
Register: CONFIG5H @ 0x300009

CPD = Data EEPROM Code Protection bit
OFF Data EEPROM not code-protected
ON Data EEPROM code-protected
CPB = Boot Block Code Protection bit
OFF Boot block (000000-0007FFh) not code-protected
ON Boot block (000000-0007FFh) code-protected
Register: CONFIG6L @ 0x30000A

WRT0 = Write Protection bit
OFF Block 0 (000800-001FFFh) not write-protected
ON Block 0 (000800-001FFFh) write-protected
WRT1 = Write Protection bit
OFF Block 1 (002000-003FFFh) not write-protected
ON Block 1 (002000-003FFFh) write-protected
WRT2 = Write Protection bit
OFF Block 2 (004000-005FFFh) not write-protected
ON Block 2 (004000-005FFFh) write-protected
WRT3 = Write Protection bit
OFF Block 3 (006000-007FFFh) not write-protected
ON Block 3 (006000-007FFFh) write-protected
Register: CONFIG6H @ 0x30000B

WRTB = Boot Block Write Protection bit
OFF Boot block (000000-0007FFh) not write-protected
ON Boot block (000000-0007FFh) write-protected
WRTC = Configuration Register Write Protection bit
OFF Configuration registers (300000-3000FFh) not write-protected
ON Configuration registers (300000-3000FFh) write-protected
WRTD = Data EEPROM Write Protection bit
OFF Data EEPROM not write-protected
ON Data EEPROM write-protected
Register: CONFIG7L @ 0x30000C

EBTR0 = Table Read Protection bit
OFF Block 0 (000800-001FFFh) not protected from table reads executed in other blocks
ON Block 0 (000800-001FFFh) protected from table reads executed in other blocks
EBTR1 = Table Read Protection bit
OFF Block 1 (002000-003FFFh) not protected from table reads executed in other blocks
ON Block 1 (002000-003FFFh) protected from table reads executed in other blocks
EBTR2 = Table Read Protection bit
OFF Block 2 (004000-005FFFh) not protected from table reads executed in other blocks
ON Block 2 (004000-005FFFh) protected from table reads executed in other blocks
EBTR3 = Table Read Protection bit
OFF Block 3 (006000-007FFFh) not protected from table reads executed in other blocks
ON Block 3 (006000-007FFFh) protected from table reads executed in other blocks
Register: CONFIG7H @ 0x30000D

EBTRB = Boot Block Table Read Protection bit
OFF Boot block (000000-0007FFh) not protected from table reads executed in other blocks
ON Boot block (000000-0007FFh) protected from table reads executed in other blocks
Register: IDLOC0 @ 0x200000

Register: IDLOC1 @ 0x200001

Register: IDLOC2 @ 0x200002

Register: IDLOC3 @ 0x200003

Register: IDLOC4 @ 0x200004

Register: IDLOC5 @ 0x200005

Register: IDLOC6 @ 0x200006

Register: IDLOC7 @ 0x200007
 

Thanks Jayanth for sparing a moment from your precious time.It was a great help. I implemented what i comprehend from above but the following problem arises
Code: 
         #pragma config IESO = OFF, OSC = RC, FCMEN = OFF
	#pragma config WDT = OFF, PWRT = ON, BOR = OFF

HTML: 
Warning [335] D:\MICRO-CONTROLER\PIC\projects\pickit test\testA.c; 8.1 unknown pragma "config"
Warning [335] D:\MICRO-CONTROLER\PIC\projects\pickit test\testA.c; 8.1 unknown pragma "IESO"
Warning [335] D:\MICRO-CONTROLER\PIC\projects\pickit test\testA.c; 8.1 unknown pragma "="
Warning [335] D:\MICRO-CONTROLER\PIC\projects\pickit test\testA.c; 8.1 unknown pragma "OFF"
Warning [335] D:\MICRO-CONTROLER\PIC\projects\pickit test\testA.c; 8.1 unknown pragma "OSC"
Warning [335] D:\MICRO-CONTROLER\PIC\projects\pickit test\testA.c; 8.1 unknown pragma "="
Warning [335] D:\MICRO-CONTROLER\PIC\projects\pickit test\testA.c; 8.1 unknown pragma "RC"
Warning [335] D:\MICRO-CONTROLER\PIC\projects\pickit test\testA.c; 8.1 unknown pragma "0xFFFF"
Warning [335] D:\MICRO-CONTROLER\PIC\projects\pickit test\testA.c; 8.1 unknown pragma "="
Warning [335] D:\MICRO-CONTROLER\PIC\projects\pickit test\testA.c; 8.1 unknown pragma "OFF"
same is the case with WDT,PWRT,BOR. the code however compiles.As these are config settings so will warnings effect code?
similarly
Code: 
__CONFIG(1, RC  & FCMDIS & IESODIS);   //undefined RC,RCIO6    gives error



Would you kindly spare a few minutes thankx.If i am forgetting or leaving something from your documentation
 

Something like this works?

__CONFIG(1, INTIO & FCMDIS & IESODIS); // 1H
__CONFIG(2, WDTPS256 & WDTDIS & PWRTEN & BOREN & BORV42); // 2H 2L

or

__CONFIG(1,0x0200);
__CONFIG(2,0X1E1F);
__CONFIG(3,0X8100);
__CONFIG(4,0X00C1);
__CONFIG(5,0XC00F);

or

#pragma config WDT = OFF, LVP = OFF, OSC = RCIO6


or

__CONFIG _CONFIG1L, _PLLDIV_1_1L & _CPUDIV_OSC1_PLL2_1L & _USBDIV_1_1L
__CONFIG _CONFIG1H, _FOSC_HS_1H & _FCMEN_ON_1H & _IESO_OFF_1H
__CONFIG _CONFIG2L, _PWRT_OFF_2L & _BOR_OFF_2L & _BORV_3_2L & _VREGEN_OFF_2L
__CONFIG _CONFIG2H, _WDT_OFF_2H & _WDTPS_1_2H
__CONFIG _CONFIG3H, _MCLRE_ON_3H & _LPT1OSC_OFF_3H & _PBADEN_OFF_3H & _CCP2MX_OFF_3H
__CONFIG _CONFIG4L, _DEBUG_OFF_4L & _LVP_OFF_4L & _STVREN_OFF_4L
__CONFIG _CONFIG5L, _CP0_OFF_5L & _CP1_OFF_5L & _CP2_OFF_5L
__CONFIG _CONFIG5H, _CPB_OFF_5H
__CONFIG _CONFIG6L, _WRT0_OFF_6L & _WRT1_OFF_6L & _WRT2_OFF_6L
__CONFIG _CONFIG6H, _WRTB_OFF_6H & _WRTC_OFF_6H & _WRTD_OFF_6H
__CONFIG _CONFIG7L, _EBTR0_OFF_7L & _EBTR1_OFF_7L & _EBTR2_OFF_7L



Zip and send mplab project files. I will see if I can make it work.

https://www.microchip.com/forums/m533726-print.aspx
 
Last edited:

The attachment is as follow. kindly spare a few moments for it .Thanks in advance
 

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  • pickit test.rar
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