Error (suppressible): (vsim-SDF-3250) /home/user1/CAD/final/netlist1.sdf(22): Failed to find INSTANCE '\data_delayed_reg[x] '.

[mohamis288]

Hello,

I want to simulate netlist.v file(generated from Synopsys), testbench file and tcbn65lp.v file in modelsim. But the following error pops up:

I can not find U4 and data_delayed_reg[x] file nor in the original Verilog code neither in the testbench file. How can I resolve this error?

Best regards

 

[dpaul]

All I can say for now is that make sure all the associated source files are present and added to your project. This is one of the most common mistakes.

--- Updated Feb 15, 2023 ---

@mohamis288 ,

Additionally, please clear your fundamentals before using this forum as a debugging tool!
(In one of your previous posts you didn't even know that a variable needs to be declared before it can be used....this is very very basic level stuff).