ERROR (SPECTRE-16385): There were 7 attempts to find the DC solution.

we design a 12bits 200M 130nm AD ,each stage can pass simulation,two or three also can,but if I simulate with more than 4 stages,it can not simulate with the error:

Error found by spectre during IC analysis, during transient analysis `tran'.
ERROR (SPECTRE-16385): There were 7 attempts to find the DC solution. In some of those attempts, a signal exceeded the blowup limit of its quantity. The last signal that failed is I(V17) = 1.63393 GA, for which the quantity is `I' and the blowup limit is (1 GA). It is possible that the circuit has no DC solution. If you really want signals this large, set the `blowup' parameter of this quantity to a larger value.
ERROR (SPECTRE-16080): No DC solution found (no convergence).

The values for those nodes that did not converge on the last Newton iteration are given below. The manner in which the convergence criteria were not satisfied is also given.
Failed test: | Value | > RelTol*Ref + AbsTol

Top 10 Solution too large Convergence failure:
I(V9) = -7.08587 mA
update too large: | 45.036 MA | > 35.4293 uA + 1 pA
I(I6.V8) = -4.90117 pA
update too large: | -220.308 mA | > 24.5059 fA + 1 pA
I(V3) = 91.2396 mA
update too large: | 45.036 MA | > 456.198 uA + 1 pA
I(V5) = -93.1172 mA
update too large: | -45.036 MA | > 465.586 uA + 1 pA
I(V13) = 30.4751 mA
update too large: | -9.97339 MA | > 152.376 uA + 1 pA
I(V4) = -184.357 mA
update too large: | -45.036 MA | > 921.784 uA + 1 pA
V(I17.I62.NM3.main:int_d) = -68.0096 uV
update too large: | -1.2 V | > 340.048 nV + 1 uV
V(I17.I60.NM3.main:int_d) = -68.0096 uV
update too large: | -1.2 V | > 340.048 nV + 1 uV
V(I17.I61.NM3.main:int_d) = -68.0096 uV
update too large: | -1.2 V | > 340.048 nV + 1 uV
V(I17.I59.NM3.main:int_d) = -68.0096 uV
update too large: | -1.2 V | > 340.048 nV + 1 uV
Top 10 Residue too large Convergence failure:
V(I6.I0.NM55.main:int_s) = -447.664 mV
residue too large: | 1.02958 TA | > 5.14791 GA + 1 pA
V(I6.I0.NM101.main:int_s) = -447.664 mV
residue too large: | 257.373 GA | > 1.28686 GA + 1 pA
V(I6.I0.NM111.main:int_s) = -447.664 mV
residue too large: | 260.41 GA | > 1.30205 GA + 1 pA
V(I6.I0.NM90.main:int_s) = -447.664 mV
residue too large: | 260.41 GA | > 1.30205 GA + 1 pA
V(I6.I0.NM53.main:int_s) = -447.664 mV
residue too large: | 498.907 GA | > 2.49453 GA + 1 pA
V(I6.I0.NM15.main:int_s) = -447.664 mV
residue too large: | 257.37 GA | > 1.28685 GA + 1 pA
V(I6.I0.NM3.main:int_s) = -447.664 mV
residue too large: | 257.37 GA | > 1.28685 GA + 1 pA
V(I6.I0.m1_3) = 9.25315 V
residue too large: | -6.79754 TA | > 33.9877 GA + 1 pA
V(I6.I0.NM50.main:int_s) = -447.664 mV
residue too large: | 458.582 GA | > 2.29291 GA + 1 pA
V(I6.I0.NM87.main:int_s) = -447.664 mV
residue too large: | 252.67 GA | > 1.26335 GA + 1 pA


The following set of suggestions might help you avoid convergence difficulties. Once you have a solution, write it to a nodeset file using the `write' parameter and read it back in on subsequent simulations using the `readns' parameter.

1. Evaluate and resolve any notice, warning, or error messages.
2. Perform sanity check on the parameter values using the parameter range checker (use ``+param param-limits-file'' as a command line argument) and heed any warnings. Print the minimum and maximum parameter value using the `info' analysis. Ensure that the bounds given for instance, model, output, temperature-dependent, and operating-point (if possible) parameters are reasonable.

3. Check the direction of both independent and dependent current sources. Convergence problems might result if current sources are connected such that they force current backward through diodes.

4. Enable diagnostic messages by setting option `diagnose=yes'.
5. Small floating resistors connected to high impedance nodes might cause convergence difficulties. Avoid very small floating resistors, particularly small parasitic resistors in semiconductors. Instead, use voltage sources or iprobes to measure current.
6. If you have an estimate of what the solution should be, use nodeset statements or a nodeset file and set as many nodes as possible.
7. Use realistic device models. Check all component parameters, particularly nonlinear device model parameters, to ensure that they are reasonable.
8. If simulating a bipolar analog circuit, ensure the region parameter on all transistors and diodes is set correctly.
9. Loosen tolerances, particularly absolute tolerances like `iabstol' (on options statement). If tolerances are set too tight, they might preclude convergence.
10. Increase the value of gmin (on options statement).
11. Use numeric pivoting in the sparse matrix factorization by setting `pivotdc=yes' (on options statement). Sometimes, it is also necessary to increase the pivot threshold to somewhere in the range of 0.1 to 0.5 using `pivrel' (on options statement).
12. Try to simplify the nonlinear component models in order to avoid regions in the model that might contribute to convergence problems.
13. Divide the circuit into smaller pieces and simulate them individually, but ensure that the results will be close to what they would be if you had simulated the whole circuit. Use the results to generate nodesets for the whole circuit.
14. If all else fails, replace the DC analysis with a transient analysis and modify all the independent sources to start at zero and ramp to their DC values. Run the transient analysis well beyond the time when all the sources have reached their final value (remember that transient analysis is very cheap when all of the signals in the circuit are not changing) and write the final point to a nodeset file. To make the transient analysis more efficient, set the integration method to backward Euler (`method=euler') and loosen the local truncation error criteria by increasing `lteratio', say to 50. Occasionally, this approach will fail or be very slow because the circuit contains an oscillator. Often times the oscillation can be eliminated for the sake of finding the dc solution by setting the minimum capacitance from each node to ground (`cmin') to a large value.



why?who can help me?

my email: jxyang1005@gmail.com

This is a very simple thing to fix. Have your supplies, VDDA VDDD VCM and have them all ramp up. Therefore, all start at zero, hold for 10ns then ramp up, say 50ns to supple.

If you do this, this will solve your error!

JGK

Hi,I set all the sources to zero,then I run it again,the error appear again.
Thank You.

Look for floating nodes within your design or an open idea current source which is not connected to anything.

JGK

it doesn't have any floating nodes or open current .it's a pipeline ADC,if put SHA,stage1&stage2,it can pass simulation,if I put stage3 behind£¬the error appear.Why?
Thank You!
JXY

In the sample and hold area there is thus a floating node. AKA after sampling =>holding. put an ideal resistors to ground of 1Gohm or even a 1Tohm. This should help it converge. If you still have a problem put a large resistor in every sample and hold circuit.

JGK