error on VHDL program....

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energy_baz

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hi,

could anyone help me to fix this error...the error state : Found 0 definitions for operator "+"...thanks
 
Last edited:

wire1 is a std_logic. wire1(n downto n) is a 1 bit unsigned value. "+" is not defined for unsigned+std_logic, but for unsigned+unsigned (and unsigned+integer).
 

so, I have to convert wire1 into unsigned/integer is it..?
 

try using wire1(n downto n) for a 1 bit unsigned array, and it should work.
 
thanks...it's work now...
 

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