Error on readign a .db file!

jgnr · Dec 11, 2012

Hello folks,

I'm using the book "Advanced-ASIC-Chip-Synthesis-Using-Synopsys-Design-Compiler-Physical-Compiler-and-Primetime-2nd-E" and i'm trying to do the logical synthesis of some block wich uses other sub-blocks.

So, first of all i'm using a script to synthesize the sub-block that works good.
At the final os this script i'm generating two files:

A .v containig the description mapped to the technology; and
A .db file thats will be used to synthesize the top blocks (that are sub blocks from my top level).

Just to understand i'm presenting an hierarchy:

TOP_LEVEL
TOP_BLOCKS
SUB_BLOCKS

Ok, the script i'm using for the top block is:

Code:

set active_design fulladder_npp_2Bits

set sub_modules {fulladder fulladder_npp}

foreach module $sub_modules {
	set syn_db $module.db
	read_db $syn_db
}
...

When i type the command read_db $syn_db the tool doesn't read them.

The error:

Error: Cannot read file 'fulladder.db'. (UID-58)
Loaded 0 designs.
Error: Cannot read file 'fulladder_npp.db'. (UID-58)
Loaded 0 designs.

I added the path where the .db are located, try to put in the same folder where i'm oppening dc_shell but nothing works.

Someone may help me?

Thanks.

mail4idle2 · Dec 11, 2012

please provide your search path

yx.yang · Dec 12, 2012

Try to copy (or link) the fulladder.db and fulladder_npp.db to the directory where you invoke dc_shell.
If this works, you need check your "set search_path" command.

jgnr · Dec 13, 2012

Sorry about my late for answering.

I tryed put the .db file in the same directory that i invoke dc_shell but the same error occurred.

I'll put the code i'm using on .synopsys_dc.setup:

Code:

set search_path		[list ../../XFAB018 ../RTL /DB_SV]
set target_library	[list D_CELLSL_LP3MOS_typ_1_80V_25C.db]
set link_library	[list {*} D_CELLSL_LP3MOS_typ_1_80V_25C.db]
set symbol_library	[list D_CELLSL.sdb]
#set physical_library	[list .pdb]

define_name_rules BORG -allowed {A-Za-z0-9} -first_restricted "_" -last_restricted "_" -max_length 30 -map {{"*cell*", "mycell"}, {"*-return", "myreturn"}}

set bus_naming_style			%s[%d]
set verilog_no_tri 			true
set verilogout_show_unconnected_pins	true
set test_default_scan_style		multiplexed_flip_flop

And here are the code i'm using to make the synthesis of top levels and top block:

Code:

set active_design fulladder_npp_2Bits

set sub_modules {fulladder fulladder_npp}

foreach module $sub_modules {
	set syn_db $module.db
	read_db $syn_db
}

analyse -format sverilog $active_design.sv
elaborate $active_design

current_design $active_design

link
uniquify

set_wire_load_mode enclosed

[B]#create_clock -period 65 -waveform [list 0 32.5] clk
#set_clock_latency 2.0 [get_clocks clk]
#set_clock_uncertainty -setup 3.0 [get_clocks clk]
#set_clock_transition 0.1 [get_clocks clk]
#set_dont_touch_network [list clk reset][/B]

set_driving_cell -cell BTHCLX8 [all_inputs]
[B]#set_drive 0 [list clk reset][/B]

[B]#set_input_delay 20.0 -clock clk -max [all_inputs]
#set_output_delay 10.0 -clock clk -max [all_outputs][/B]

[I]set_input_delay 20.0 -max [all_inputs]
set_output_delay 10.0 -max [all_outputs][/I]

set_max_area 0

set_fix_multiple_port_nets -all -buffer_constants

compile -scan

remove_attribute [find -hierarchy design {"*"}] dont_touch

current_design $active_design
uniquify

check_test
create_test_patterns -sample 10
preview_scan
insert_scan
check_test
compile -only_design_rule

remove_unconnected_ports [find -hierarchy cell {"*"}]
change_names -hierarchy -rules BORG

set_dont_touch $active_design

write -hierarchy -output $active_design.db
write -format verilog -hierarchy -output $active_design.sv

So, the bold code means that, as i'm synthesising non clocked blocks i just coment those lines.
The italic code is used to put the I/O delays but without the clock.

Three other comments about the code:

-There're some codes that are not supported anymore for some versions of design_compiler as 'check_test', do you know any other way to do this?
-When the dc_shell intializes appears the message:
Initializing...
Error: unknown command '%d' (CMD-005)
Coul be something on the .setup file?

-There is any other adjustments that i need to do to sinthesize unclocked block?

PS: Sorry about the grammar, i'm brazilian and hope you understand. Bye Thanks for everything.

oratie · Dec 13, 2012

Add your working directory (where you've copied your .db files) in the search_path. For example "set search_path ". $search_path" (the char "." means the current directory).

jgnr · Dec 13, 2012

The .db file are located inside of the directory DB_SV.
I added it on the search_path before i post here, and error occurred already.

Some help?

Thanks oratie.

yx.yang · Dec 14, 2012

Hi, I think you need try the following:
1:
set search_path [list ../../XFAB018 ../RTL ./DB_SV]; ## not "/DB/SV
And designer always add the directory you invoke DC to the search path: set search_path [list . ../../XFAB018 ../RTL ./DB_SV];

2: Modify your read_db command. read_db ./DB_SV/$syn_db ; ## or for debug purpose: read_db ./DB_SV/fulladder.db

PS: And there seems a error in your .setup file. Try the following:set bus_naming_style {%s[%d]} ; ## and {} to disable tcl recognise [] as a calling of some command.

jgnr · Dec 14, 2012

yx.yang said:
Hi, I think you need try the following:
1:
set search_path [list ../../XFAB018 ../RTL ./DB_SV]; ## not "/DB/SV
And designer always add the directory you invoke DC to the search path: set search_path [list . ../../XFAB018 ../RTL ./DB_SV];

2: Modify your read_db command. read_db ./DB_SV/$syn_db ; ## or for debug purpose: read_db ./DB_SV/fulladder.db

PS: And there seems a error in your .setup file. Try the following:set bus_naming_style {%s[%d]} ; ## and {} to disable tcl recognise [] as a calling of some command.

Thanks yang, both steps help me, but now the tools return this message:

Error: File is not a DB file. (DB-1)
Error: The file '/home/joaonizer/filtros/slogica/018/teste/work/DB_SV/fulladder.db' is not a DB file.
No designs were read

But this files were generated by the own tool when i sintesized this blocks before.

Thanks until now.

yx.yang · Dec 17, 2012

Hi, Please try the "man write_file" command (write_file will replace write in the future).
Then the default write out format will be "ddc" format.
So you may:
1): write_files -format ddc -hierarchy -output $active_design.db
Or:
2): read_ddc or read_files -format ddc.
For any command, you can use "man command_name" to get more info about this command and the related commands.

jgnr · Jan 8, 2013

So,

I tryed to use de comand write -format ddc -hierarchy -output $active_design.db

It generated the .db files but this files were not read by the tool as before.

I tryed to use de command:

write -format db -hierarchy -output $active_design.db

But the tool returns this error:
Error: Writing designs in DB format is no longer supported. (UID-530)

Since 2007.03 versions of synthesis tools do not support db files anymore, and i didn't find any other versions before 2009.

So thanks for help.

Unless you have any other consideration to do i will try find other ways to do the synthesis without using .db files and close this thread.

Thanks.

Error on readign a .db file!

jgnr

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mail4idle2

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yx.yang

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jgnr

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oratie

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