I would like to ask help regarding this error from the layout.
I using TSMC 0.18um 1P6M process.
My design requires an NMOS with a shorted source and bulk.
I would like to ask help regarding this error from the layout.
I using TSMC 0.18um 1P6M process.
My design requires an NMOS with a shorted source and bulk.
If you put NMOS in a DNW/VNW pocket then its body is cut
off from the bulk / handle Psub and you will have to route the
body (tap) explicitly to open field and a ptap there.
What value do you imagine putting it in a DNW pocket is,
when you intend to jumper it to the substrate in the end?
You eat a lot of layout area for nothing (except perhaps
substrate noise control).
If you put NMOS in a DNW/VNW pocket then its body is cut
off from the bulk / handle Psub and you will have to route the
body (tap) explicitly to open field and a ptap there.
What value do you imagine putting it in a DNW pocket is,
when you intend to jumper it to the substrate in the end?
You eat a lot of layout area for nothing (except perhaps
substrate noise control).
So then you do not want source tied to "bulk" (which is the
handle Psub / Pepi) but the local body "pocket" (Pepi inside
DNW/VNW). That may want you to use a 4T FET symbol and
wire it explicitly; the 3T may have an inherited sub! connection
that you either can't modify or can't find?