Error: Ngdbuild: 455 and error Ngdbuild: 466

ngdbuild:455

Hi all

does any body around here have any idea to deal with this problem.
I'm using ISE webpack 5.2 upgraded to 5.2.03. Synthesis is ok while going for translation NDGBuild gives this error.

ERROR:NgdBuild:455 - logical net 'cclk' has multiple drivers. The possible
drivers causing this are pin O on block ibufg_x with type IBUFG, pin PAD on block cclk with type PAD

ERROR:NgdBuild:466 - input pad net 'cclk' has illegal connection. Possible pins causing this are pin O on block ibufg_x with type IBUFG.



i dont know that to do with these errors and how to resolve these errors.
the net cclk has been defined as a signal and is the output of a Global clock buffer IBUFG.

Also that related to multiple drivers this signal bieng an output from Ibufg is given as an input to the component as a clock which is giving this error.

if anyone around here knows about this problem and solution help me out of the situation.

regards
Ashish

error:ngdbuild:455

Hi,

I don't know if its possible to put the ouput of a IBUFG on an output pin of your FPGA, and to use it as a clock in the design. The Builder may try to put the signal in IO pad and so cannot use it as an internal clock ...
May be you have to generate 2 BUFG with the same input. one output will be used as internal clock, the other as an output.
Use the attribute to avoid synthesis symplification (with XST):

attribute keep : string;
attribute keep of cclk1 : signal is "true";
attribute keep of cclk2 : signal is "true";

I hope this will help you...

error:ngdbuild:455 - logical net

hi
thanks for the help and suggestion. actually i figured out the problem and solved it out. what thing was giving problem was that at the input there was laready a buffer i.e. bufg which i didnot knew but came to know later, and i was trying to provide another global clock buffer i.e. ibufg. i resolved that out. anyways thanks again.

regards
ashish