keshexinxin
Newbie level 5
help DFT question?
Now I use the synopsys DFT to add scan chain after synthesis the verilog code.
before I insert_scan . I do check_test command . and the DC give me some information like that
Information : Inferred system/test clock port XCLK(20,0,30,0).(TEST-260)
Information : Inferred system/test clock port XCLK(20,0,30,0).(TEST-260)
Information : Inferred system/test clock port XCLK(20,0,30,0).(TEST-260)
but before I check test . I define the test protocol and create only one test clock XCLK (20,0,30,0). I don't know how can I get the other two systerm clock . and how to get rid of them.
btw . I use the synopsys 2002.05 ver
thanks for help
Now I use the synopsys DFT to add scan chain after synthesis the verilog code.
before I insert_scan . I do check_test command . and the DC give me some information like that
Information : Inferred system/test clock port XCLK(20,0,30,0).(TEST-260)
Information : Inferred system/test clock port XCLK(20,0,30,0).(TEST-260)
Information : Inferred system/test clock port XCLK(20,0,30,0).(TEST-260)
but before I check test . I define the test protocol and create only one test clock XCLK (20,0,30,0). I don't know how can I get the other two systerm clock . and how to get rid of them.
btw . I use the synopsys 2002.05 ver
thanks for help