library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Project4 is
Port ( Clock : in STD_LOGIC;
Resetn : in STD_LOGIC;
R : in STD_LOGIC;
S : in STD_LOGIC;
T : in STD_LOGIC;
Z : out STD_LOGIC);
end Project4;
architecture Behavioral of Project4 is
type state_type is (A, B, C, D);
signal y : State_type;
45.begin
46.Process (Resetn, clock, )
begin
47.If resetn '0' then y<= 'A';
48.Else If ( clock' Event and Clock = '1') Then
49.Case y is
50.when A =>
51.If s = '1' and T = '1' then y <= A;
52.else If s = '1' and T = '0' then y <= B;
else If s = '0' then y <= C;
else If S= '0'; End If;
When B=>
If R= '0' then y<=B;
Else If R='1' the y<=C;
when c=>
If R='0' and T='0' then y<=B;
else if R='1' and T='1' then y<=B;
else if R='1' and T='0' then y<=A;
else if R='0' and T='1' then y<=D;
when D=>
If R='0' then y<=A;
else y<=D; end if
end case;
end if;
end process;
end Behavioral;