Error Memory in Quartus II

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flote21

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Hello guys!

I am trying to make a compilation of my project and I get this error:

Error (114016): Out of memory in module quartus_map.exe (4316 megabytes used)
Error (293007): Current module quartus_map ended unexpectedly

Anybody knows how to solve it?

Thanks.
 

What chip are you compiling for, and what are you system specs?

Basically, from the larger from Cyclone4 or arria 2 you need minimum 3 GB of ram. For stratix 4 + you need min 8 or 16 GB I think/
 
Problem solved. I reduced the memory of my VHDL arrays and it is working. I am using a cyclone IV and my PC has 12Gb of RAM and it is a Pentium I7. But I was running modelsim while launching the compilation in Quartus II. Maybe this was the reason.

TrickyDicky said:
What chip are you compiling for, and what are you system specs?

Basically, from the larger from Cyclone4 or arria 2 you need minimum 3 GB of ram. For stratix 4 + you need min 8 or 16 GB I think/
Click to expand...

- - - Updated - - -

Problem solved. I reduced the memory of my VHDL arrays and it is working. I am using a cyclone IV and my PC has 12Gb of RAM and it is a Pentium I7. But I was running modelsim while launching the compilation in Quartus II. Maybe this was the reason.
 

flote21 said:
Problem solved. I reduced the memory of my VHDL arrays and it is working.
Click to expand...

If you modifed the VHDL to get this to work - it makes me think you've written some poor quality VHDL. Any chance you could post it, and we can assess?
 

Hi! Yes I can post my VHDL code:

Code: 
  signal FPGA_MODEs     : std_logic_vector(FPGA_MODE'range);
  signal FPGA_MODE_l    : std_logic_vector(FPGA_MODE'range);
  signal RAW_DATAs      : std_logic;
  signal RAW_DATAss     : std_logic;
  signal VID_I_DAVr     : std_logic;  
  signal BIN_SEL        : unsigned(2 downto 0);  
  signal BIN_ADD1       : unsigned(15 downto 0);
  signal BIN_ADD2       : unsigned(15 downto 0);
  signal X_CNT_H        : integer RANGE 0 to 5000;    
  signal Y_CNT_H        : integer RANGE -1 to 5000;
  signal X_CNT_V        : integer RANGE 0 to 5000;      
  type ARRAY_2D is array (0 to 5,0 to 710) of unsigned (15 downto 0);
  signal	ARRAY_2Ds :	ARRAY_2D := ((others=> (others=>x"0000"))); -- intialize to 0      
  signal BIN_SELr    : unsigned(2 downto 0);  
  signal BIN_ADD3       : unsigned(18 downto 0);
  signal BIN_ADD4       : unsigned(18 downto 0);  
  signal BIN_ADD5       : unsigned(18 downto 0);  
  signal BIN_SAVE1      : unsigned(18 downto 0); 
  signal BIN_SAVE2      : unsigned(18 downto 0); 
  signal BIN_DAV        : std_logic;    

BINNING_H_proc : process(VID_I_CLK, VID_I_RST)  
  begin
    if VID_I_RST = '1' then
      FPGA_MODE_l  <= (others => '0');	
		VID_I_DAVr   <= '0';	
		BIN_DAV      <= '0';				
      BIN_ADD1     <= (others => '0');
      BIN_ADD2     <= (others => '0');
		BIN_ADD3     <= (others => '0');
		BIN_ADD4     <= (others => '0');		
		BIN_ADD5     <= (others => '0');		
		BIN_SAVE1    <= (others => '0');
		BIN_SAVE2    <= (others => '0');
		BIN_DATA     <= (others => '0');
      X_CNT_H <= 0; 		
		Y_CNT_H <= -1;		  
		X_CNT_V <= 0;
	   ARRAY_2Ds <= ((others=> (others=>x"0000")));
      VID_F_SOI   <= '0';
      VID_F_SOL   <= '0';
		BIN_SEL     <= (others => '0');      		
		BIN_SELr    <= (others => '0');      		
    elsif rising_edge(VID_I_CLK) then

     -- Latch Dropping Factors + Reset Counters
	  VID_F_SOI  <= '0';
     if VID_I_SOI = '1' then
        FPGA_MODE_l <= FPGA_MODEs;  -- Latching Binning Mode  
        VID_F_DARK <= VID_I_DARK; -- Latch Dark Info		  
		  if RAW_DATAss = '1' then
				VID_F_SOI  <= '1';
		  else
			  BIN_SEL   <= (others => '0');			 			 			 			      	  
			  ARRAY_2Ds <= ((others=> (others=>x"0000")));
			  BIN_ADD1  <= (others => '0');
			  BIN_ADD2  <= (others => '0');
			  X_CNT_H <= 0;		  
			  Y_CNT_H	 <= -1;
			  VID_I_DAVr <= '0';		  		  
		  end if;
     end if;	  

     -- Valid Lines Management      
	  VID_F_SOL <= '0';	  
     if VID_I_SOL = '1' then   -- New line	   		
      if RAW_DATAss = '1' then
			VID_F_SOL <= '1'; -- Output every line          
		else
	 		-- Increment ARRAY_2Ds_Y		
			Y_CNT_H	 <= Y_CNT_H + 1;
			-- Reset ARRAY_2Ds_X 		
			X_CNT_H <= 0;		  
		end if;
    end if;

	 
      -- Valid Pixels Management :
      -- Receiving 4 pixels on every clock cycle      				
      if VID_I_DAV = '1' then  -- New "4pixels" 	          
		  BIN_SEL    <= BIN_SEL + 1;
        -- Binning 6x6
        if FPGA_MODE_l = "100" then 
          if BIN_SEL = 2 then 
            BIN_SEL <= "000";			   
          end if;		  
          if BIN_SEL = 0 then			 
				BIN_ADD1 <= resize(unsigned(VID_I_DATA(11 downto 00)), BIN_ADD1'length) + unsigned(VID_I_DATA(35 downto 24));
				BIN_ADD2 <= resize(unsigned(VID_I_DATA(23 downto 12)), BIN_ADD2'length) + unsigned(VID_I_DATA(47 downto 36));          			 			 				
				X_CNT_H <= X_CNT_H + 1;																																					 
			 elsif BIN_SEL = 1 then			 
 				BIN_ADD1 <= resize(unsigned(VID_I_DATA(35 downto 24)), BIN_ADD1'length); 			 
				BIN_ADD2 <= resize(unsigned(VID_I_DATA(47 downto 36)), BIN_ADD2'length);
				--
				ARRAY_2Ds(Y_CNT_H, X_CNT_H-1) <=  BIN_ADD1 + resize(unsigned(VID_I_DATA(11 downto 00)), BIN_ADD1'length);
				ARRAY_2Ds(Y_CNT_H, X_CNT_H)   <=  BIN_ADD2 + resize(unsigned(VID_I_DATA(23 downto 12)), BIN_ADD2'length);				 
				X_CNT_H <= X_CNT_H + 1;																																					 
			 elsif BIN_SEL = 2 then			 
				ARRAY_2Ds(Y_CNT_H, X_CNT_H)   <=  BIN_ADD1 + resize(unsigned(VID_I_DATA(11 downto 00)), BIN_ADD1'length) 
				                                           + resize(unsigned(VID_I_DATA(35 downto 24)), BIN_ADD1'length);
				ARRAY_2Ds(Y_CNT_H, X_CNT_H+1) <=  BIN_ADD2 + resize(unsigned(VID_I_DATA(23 downto 12)), BIN_ADD2'length)
																		 + resize(unsigned(VID_I_DATA(47 downto 36)), BIN_ADD2'length);				 			 								                                           
				X_CNT_H <= X_CNT_H + 2;																																					 
			 end if;			 
			 if Y_CNT_H = 5 and X_CNT_H = 2 then -- Ready to provide RGB psixels!
				VID_I_DAVr <= '1';
				VID_F_SOI  <= '1';
			 end if;
		 end if;
	  end if;
	
	  
	  -- Adding pixels using pipeline techniques	  	  
	  BIN_DAV  <= '0';	  
     if VID_I_DAVr = '1' then  
	  BIN_SELr    <= BIN_SELr + 1;
		 -- Binning 6x6
	    if FPGA_MODE_l = "100" then								
         if BIN_SELr = 4 then 
           BIN_SELr <= "001";
         end if;	  			
			--
			if BIN_SELr = 0 then		
				VID_F_SOL <= '1';
			elsif BIN_SELr = 1 then		
				BIN_DAV <= '1'; 		
				BIN_DATA <= std_logic_vector(resize(ARRAY_2Ds(1,X_CNT_V), BIN_DATA'length) + 
				                             ARRAY_2Ds(3,X_CNT_V)+ ARRAY_2Ds(5,X_CNT_V));
			elsif BIN_SELr = 2 then
				BIN_DAV <= '1'; 
				BIN_DATA <= std_logic_vector(resize(ARRAY_2Ds(0,X_CNT_V+1), BIN_DATA'length) + 
				                             ARRAY_2Ds(2,X_CNT_V+1) + ARRAY_2Ds(4,X_CNT_V+1));
			elsif BIN_SELr = 3 then				
				BIN_DATA <= std_logic_vector(resize(ARRAY_2Ds(0,X_CNT_V), BIN_DATA'length)   +
													  ARRAY_2Ds(2,X_CNT_V)   + ARRAY_2Ds(4,X_CNT_V)   +
							                    ARRAY_2Ds(1,X_CNT_V+1) + ARRAY_2Ds(3,X_CNT_V+1) + 
													  ARRAY_2Ds(5,X_CNT_V+1));
			elsif BIN_SELr = 4 then
				BIN_DAV <= '1'; 
				BIN_DATA <= '0' & BIN_DATA(BIN_DATA'length-1 downto 1);
				X_CNT_V <= X_CNT_V + 2;	
			end if;	
			--
			if X_CNT_V >= LIMIT_X_CNT_6R then
				VID_I_DAVr <= '0';				
				BIN_SELr  <= (others => '0');      		
				BIN_ADD3  <= (others => '0');
				BIN_ADD4  <= (others => '0');				
				BIN_ADD5  <= (others => '0');				
				BIN_SAVE1 <= (others => '0');
				BIN_SAVE2 <= (others => '0');
				BIN_DATA  <= (others => '0');								
				X_CNT_V   <= 0; 
			end if;	 	
		end if;		
	 end if;	 	 
	  	
 end if;
end process BINNING_H_proc;

TrickyDicky said:
If you modifed the VHDL to get this to work - it makes me think you've written some poor quality VHDL. Any chance you could post it, and we can assess?
Click to expand...
 

Code: 
  signal	ARRAY_2Ds :	ARRAY_2D := ((others=> (others=>x"0000"))); -- intialize to 0

You want to ARRAY_2Ds to be ram or what ?
 


So then this stuff expains why it delays around 1 hour to synthesis the code and when I try to make the fitter it does not work and Quartus II gives me an Error. What can I do to have the same working like an ARRAY_2D? Maybe a RAM?

 

flote21 said:
So then this stuff expains why it delays around 1 hour to synthesis the code and when I try to make the fitter it does not work and Quartus II gives me an Error. What can I do to have the same working like an ARRAY_2D? Maybe a RAM?
Click to expand...
It takes a while to build those 68,256 bits in your array. If you have a 2D array that is say bigger than 1Kb (8x8x16-bit, sort of an arbitrary limit ;-)) then you're likely coding something that should be using a RAM block.
 

You mean that if I declare an array 2d like this:

type ARRAY_2D is array (0 to 7,0 to 1023) of unsigned (15 downto 0);

Should it work fine? Now everything is pow of 2....

ads-ee said:
It takes a while to build those 68,256 bits in your array. If you have a 2D array that is say bigger than 1Kb (8x8x16-bit, sort of an arbitrary limit ;-)) then you're likely coding something that should be using a RAM block.
Click to expand...
 

No. Using a 2d array will not infer a ram from your VHDL. He is just saying you should probably re-design your code so that a ram is infered (ie. you probably want a ram, not a load of registers).

Did you read through the altera coding guidelines for ram inference? it explains quite clearly the code templates you need to infer different types of ram.
 

In hardware terms, a 2D-array isn't but an address mapping. It's quite easy to define an 1D-array with N*M elements and use a function to calculate the 1D index from 2D indices.
 

mmmm I have to think about this last issue....But I have another problem added and it is the space available in my FPGA (cyclone IV) I need a RAM of 65Kb to do a data processing and over 1Kb the FPGA is full...
 

Your 2D array needs about 60 -100 kbits (depending on the mapping method). Even the smallest Cyclone IV device has 270 kbits available. In so far there shouldn't be a problem if you finally manage to infer RAM instead of LE registers.
 

Have you looked at the synthesis report. That will show you what resources will likely be required. I suspect you are running out of LEs due to the 68Kb of 'RAM' i.e. flip-flops getting implemented by that 2D array.
 

Ok. I hae already solved my problem. I used several dual port RAMs and I have optimized the VHDL coding. Now everything is working fine and it fits in the FPGA. It was a bad practic VHDL designing.

Thanks a lot people!

ads-ee said:
Have you looked at the synthesis report. That will show you what resources will likely be required. I suspect you are running out of LEs due to the 68Kb of 'RAM' i.e. flip-flops getting implemented by that 2D array.
Click to expand...
 

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