Error message in Synopsys DFT after check_test

[keshexinxin]

help DFT question?

Now I use the synopsys DFT to add scan chain after synthesis the verilog code.

before I insert_scan . I do check_test command . and the DC give me some information like that

Information : Inferred system/test clock port XCLK(20,0,30,0).(TEST-260)
Information : Inferred system/test clock port XCLK(20,0,30,0).(TEST-260)
Information : Inferred system/test clock port XCLK(20,0,30,0).(TEST-260)

but before I check test . I define the test protocol and create only one test clock XCLK (20,0,30,0). I don't know how can I get the other two systerm clock . and how to get rid of them.

btw . I use the synopsys 2002.05 ver

thanks for help

 

[keshexinxin]

oh sorry . I make a mistake about the information .

the information like this

Information : Inferred system/test clock port XCLK(20,0,30,0).(TEST-260)
Information : Inferred system/test clock port CPU_ADDR[1](22,5,27,5).(TEST-260)
Information : Inferred system/test clock port CONF[1](22,5,27,5).(TEST-260)

 

[alanray]

TESTCLK GEN

Did your design have internal gate clock

 

[johnnyh]

please post your script file, just the error message cannot debug.