srini.pes
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Dear all
In my transient analysis am getting this error.
my input pulse is like PULSE (0 0.9 0 5N 5N 150N 300N)
and my
.tran 10N 500N UIC
**error** internal timestep too small in transient analysis
time = 0.80000E-11; delta = 0.37253E-22; numnit = 32168
1****** HSPICE -- C-2009.03-SP1 32-BIT (May 25 2009) winnt ******
.options reltol=0.01 vntol=1e-06 abstol=1e-9
.options post
.options node list
.options method=gear
.options TRCON=0
.option brief=0
.OPTIONS METHOD=GEAR
.options AUTOSTOP
.options INGOLD=2 DCON=1
.options GSHUNT=1e-12 RMIN=1e-15
.options ABSTOL=1e-5 ABSVDC=1e-4
.options RELTOL=1e-2 RELVDC=1e-2
.options NUMDGT=4 PIVOT=13
These are the options i have used in spice file.
My design is a 4-bit adder, when i simulated for 2-bit adder, it was working fine
when i simulated for 4-bit only it was showing error.
Please clarify.
--------------
Thanks
SRINI
In my transient analysis am getting this error.
my input pulse is like PULSE (0 0.9 0 5N 5N 150N 300N)
and my
.tran 10N 500N UIC
**error** internal timestep too small in transient analysis
time = 0.80000E-11; delta = 0.37253E-22; numnit = 32168
1****** HSPICE -- C-2009.03-SP1 32-BIT (May 25 2009) winnt ******
.options reltol=0.01 vntol=1e-06 abstol=1e-9
.options post
.options node list
.options method=gear
.options TRCON=0
.option brief=0
.OPTIONS METHOD=GEAR
.options AUTOSTOP
.options INGOLD=2 DCON=1
.options GSHUNT=1e-12 RMIN=1e-15
.options ABSTOL=1e-5 ABSVDC=1e-4
.options RELTOL=1e-2 RELVDC=1e-2
.options NUMDGT=4 PIVOT=13
These are the options i have used in spice file.
My design is a 4-bit adder, when i simulated for 2-bit adder, it was working fine
when i simulated for 4-bit only it was showing error.
Please clarify.
--------------
Thanks
SRINI