Error: Index <8> is out of range [0:7] for signal <ram>.

QMA · Aug 25, 2015

Dear all
I am trying a code in verilog with the following specs;

Code Verilog - [expand]
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integer i;
reg [4:0]R_addr;
reg [7:0]temp;
reg [7:0] ram [0:7];
R_addr = R_addr - 1'b1;
for(i = 0; i<=R_addr; i = i+1)
begin
temp = ram[i];
------
------
------
end

I am getting the subjected error while synthesizing. Please tell me why i am getting the error and how can i overcome it.

ads-ee · Aug 25, 2015

For loops in Verilog should have compile time constants for iteration limits, otherwise the code isn't synthesizable. If R_addr isn't a constant then the code won't synthesize as that would represent run time self modifying hardware.

The reason the index 8 shows up is because reg [3:0] R_adder can hold a value of 4'd0-4'd15, which is obviously larger than the ram [0:7] unpacked index.

aruipksni · Aug 25, 2015

if you just want to read from memory all you need is a mux

Code Verilog - [expand]
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assign temp = ram[R_addr];

Error: Index <8> is out of range [0:7] for signal <ram>.

QMA

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QMA

aruipksni

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Code Verilog - [expand]
1 2 3 4 5 6 7 8 9 10 11 12	integer i; reg [4:0]R_addr; reg [7:0]temp; reg [7:0] ram [0:7]; R_addr = R_addr - 1'b1; for(i = 0; i<=R_addr; i = i+1) begin temp = ram[i]; ------ ------ ------ end

Error: Index <8> is out of range [0:7] for signal <ram>.

QMA

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aruipksni

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