error in verilog output code for counter testbench

[satishbabub]

hello guys can u help me with this ?
i have written a simple verilog program for counter and its testbench as well.but the counter output either stays at one or zero rather counting . what kind of signal do u expect me to give at waveforms for reset and enable ?...here are the codes
module counter (clk,reset,enable,count);
input clk,reset,enable;
output [3:0] count;
reg count;
always @ (posedge clk or posedge reset)
if (reset) begin
count <=4'b0;
end
else
if (enable) begin
count <= count + 1'b1;
end
endmodule

module countertb();
reg clk,reset,enable;
counter u0 (clk,reset,enable,count);
initial
begin
clk=0;
reset=0;
enable=0;
end
always
#5 clk =!clk;
initial begin
$display ("\t\time,\tclk,\treset,\tenable,\tcount");
$monitor ("%d,\t%b,\t%b,\t%b,\t%b",$time,clk,reset,enable,count);
end
initial
#1000 $finish;
endmodule



im a starter in verilog ,explicit explanation is most welcome thanks

 

[paulki]

Very simple reason is your output declaration "output [3:0] count" should matched with your reg declaration. It should be "reg [3:0] count".
Otherwise as per your code, reg assignemnt on single bit and your counter could not proceed further.

-paulki

 

[Alosevskoy]

... and in the tb you need one more declaration:
module countertb();
reg clk,reset,enable;
wire [3:0] count;
counter u0 (clk,reset,enable,count);
initial
...


Good luck!

 

[satishbabub]

thanks ,found the error...