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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_arith.all;
use work.ldpc_package.all;
use work.new_min_values_package.all;
entity Message_CN_VN_new is
port(clk_external,clk_internal,reset:in bit;L:in matrix1xN;out_min_1,out_min_2:in matrix1152x1;index_min:in matrix1x1152b;sign_value:in matrix1152x7sign;
sign_each_row:in matrix1x1152sign;out_min_1_new,out_min_2_new:out matrix1152x1;index_min_new:out matrix1x1152b;
sign_value_new:inout matrix1152x7sign;sign_each_row_new:out matrix1x1152sign;col_index_nonzero:inout matrix1152x7_2304;L_new:inout matrix1xN);
end ;
architecture behave of Message_CN_VN_new is
type matrix1x12 is array (1 to 12) of integer range 7 to 8;
type matrix1x12_2304 is array (1 to 12) of matrix1x7_2304;
--subtype matrix7x96 is matrix24x96;
--subtype int is integer range -127 to 2304;
component new_min_values
port(clk_external,clk_internal,reset,clr,clr_1:in bit;L_LLR:in matrix1xn;L_matrix_row:in matrix7x96_i;L_matrix_old:in matrix96x7;length_row:in integer range 7 to 8;L:in matrix1xN;out_min_1,out_min_2:in matrix96x1;index_min:in matrix1x96b;sign_value:in matrix96x7sign;
sign_each_row:in matrix1x96sign; H,col_each_rowblock: in matrix1x7_2304;out_min_1_new,out_min_2_new:out matrix96x1;index_min_new:out matrix1x96b;
sign_value_new:inout matrix96x7sign;sign_each_row_new:out matrix1x96sign;col_index_nonzero:inout matrix96x7_2304;L_new:inout matrix1xN;L_matrix_new:out matrix96x7;clr_2,clr_0:inout bit);
end component;
component MATRIX_L
port( H_i:in matrix1x7_2304;L:in matrix1xn;L_matrix : out matrix7x96_i);
end component;
component MATRIX_L_LLR
port(clk_internal,clr:in bit;H,col_each_rowblock_i:in matrix1x7_2304;col_index_nonzero:in matrix96x7_2304;L_LLR:in matrix1xn;length_row:in integer range 7 to 8;L_matrix : out matrix96x7;clr_out:out bit);
end component;
component col_index_96
port(sum:in integer range 1 to 96;clk_external,clk,reset,clr_in:in bit;L_matrix_row:in matrix7x96_i;length_row:in integer range 7 to 8;col_each_rowblock: in matrix1x7_2304;col_index_nonzero:out matrix1x7_2304
;col_L_nonzero:out matrix1x7);
end component;
component col_index_96_clr
port(sum:in integer range 1 to 96;clk_external,clk,reset,clr_in:in bit;L_matrix_row:in matrix7x96_i;length_row:in integer range 7 to 8;col_each_rowblock: in matrix1x7_2304;col_index_nonzero:out matrix1x7_2304;
col_L_nonzero:out matrix1x7;clr_out:out bit);
end component;
component new_min_value
port(clk,clr,reset:in bit;L_matrix:in matrix1x7;col_index_nonzero:in matrix1x7_2304;col_L_nonzero:in matrix1x7;length_row:in integer range 7 to 8;out_min_1,out_min_2:in integer range 0 to 127;index_min:in bit_vector(2 downto 0);sign_value:in matrix1x7sign;
sign_each_row:in integer range -1 to 1;out_min_1_new,out_min_2_new:out integer range 0 to 127;
index_min_new:out bit_vector(2 downto 0);sign_value_new:out matrix1x7sign;sign_each_row_new:out integer range -1 to 1
;L_matrix_new:out matrix1x7);end component;
component new_min_value_clr
port(clk,clr,reset:in bit;L_matrix:in matrix1x7;col_index_nonzero:in matrix1x7_2304;col_L_nonzero:in matrix1x7;length_row:in integer range 7 to 8;out_min_1,out_min_2:in integer range 0 to 127;index_min:in bit_vector(2 downto 0);sign_value:in matrix1x7sign;
sign_each_row:in integer range -1 to 1;out_min_1_new,out_min_2_new:out integer range 0 to 127;
index_min_new:out bit_vector(2 downto 0);sign_value_new:out matrix1x7sign;sign_each_row_new:out integer range -1 to 1;L_matrix_new:out matrix1x7;clr_out:out bit
);
end component;
signal jj:integer range 0 to 100000000;
signal out_min_1_i:matrix96x1;
signal out_min_2_i:matrix96x1;
signal index_min_i:matrix1x96b;
signal sign_value_i:matrix96x7sign;
signal sign_each_row_i:matrix1x96sign;
signal H_i:matrix1x7_2304;
signal col_each_rowblock_i:matrix1x7_2304;
signal out_min_1_new_i:matrix96x1;
signal out_min_2_new_i:matrix96x1;
signal index_min_new_i:matrix1x96b;
signal sign_value_new_i:matrix96x7sign;
signal sign_each_row_new_i:matrix1x96sign;
signal ii:int:=1;
signal col_index_nonzero_i:matrix96x7_2304;
signal length_row:matrix1x12;
signal length_row_i:integer range 7 to 8;
signal H,col_each_rowblock:matrix1x12_2304;
signal clr :bit:='1';
signal clr_i:bit;
signal L_matrix_row:matrix7x96_i;
signal L_matrix_old,L_matrix_new,L_matrix_LLR:matrix96x7;
signal L_LLR:matrix1xn:=(others=>0);
signal i:integer range 1 to 7;
signal i1:integer range 1 to 8;
signal col_L_nonzero_01:matrix1x7;
signal col_L_nonzero_02:matrix1x7;
signal col_L_nonzero_03:matrix1x7;
signal L_matrix_01:matrix1x7;
signal L_matrix_02:matrix1x7;
signal L_matrix_03:matrix1x7;
signal col_index_nonzero_01:matrix1x7_2304;
signal col_index_nonzero_02:matrix1x7_2304;
signal col_index_nonzero_03:matrix1x7_2304;
signal L_matrix_new_01:matrix1x7;
signal L_matrix_new_02:matrix1x7;
signal L_matrix_new_03:matrix1x7;
signal add_01:matrix1x7_2304;
signal add_02:matrix1x7_2304;
signal add_03:matrix1x7_2304;
signal add_04:matrix1x7_2304;
signal clr_1,clr_0,clr_2,clr_out:bit;
begin
--L_matrix_00:matrix_L port map( H_i,L,L_matrix_row );
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col_index_01: col_index_96 port map(01,clk_external,clk_internal,reset,clr_i,L_matrix_row,length_row_i,col_each_rowblock_i,col_index_nonzero_01,col_L_nonzero_01);
col_index_02: col_index_96 port map(02,clk_external,clk_internal,reset,clr_i,L_matrix_row,length_row_i,col_each_rowblock_i,col_index_nonzero_02,col_L_nonzero_02);
col_index_03: col_index_96 port map(03,clk_external,clk_internal,reset,clr_i,L_matrix_row,length_row_i,col_each_rowblock_i,col_index_nonzero_03,col_L_nonzero_03);
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process(clk_internal,clr_0)
variable ii:integer range 0 to 8;
variable stop_internal:bit;
begin
if clr_0 ='0' then
ii:=0;stop_internal:='1';
else
if (clk_internal'event and clk_internal='1') then
if (stop_internal='1') then
if ii=length_row_i-1 then
ii:=length_row_i-1;
stop_internal:='0';
clr_1<='1';
else
ii:=ii+1;
clr_1<='0';
end if;
i1<=ii;
else
end if;
end if;
end if;
end process;
--add_96(i1)<=(H_i(i1)-1)*96+col_index_nonzero_96(i1);
add_01(i1)<=(H_i(i1)-1)*96+col_index_nonzero_01(i1);
add_02(i1)<=(H_i(i1)-1)*96+col_index_nonzero_02(i1);
add_03(i1)<=(H_i(i1)-1)*96+col_index_nonzero_03(i1);
--
L_matrix_01(i1)<=L_LLR(add_01(i1));
L_matrix_02(i1)<=L_LLR(add_02(i1));
L_matrix_03(i1)<=L_LLR(add_03(i1));
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new_min_value_01:new_min_value port map(clk_internal,clr_1,reset,L_matrix_01,col_index_nonzero_01,col_L_nonzero_01,length_row_i,out_min_1_i(01),out_min_2_i(01),index_min_i(01),sign_value_i(01),sign_each_row_i(01),out_min_1_new_i(01),out_min_2_new_i(01),index_min_new_i(01),sign_value_new_i(01),sign_each_row_new_i(01),L_matrix_new_01);
new_min_value_02:new_min_value port map(clk_internal,clr_1,reset,L_matrix_02,col_index_nonzero_02,col_L_nonzero_02,length_row_i,out_min_1_i(02),out_min_2_i(02),index_min_i(02),sign_value_i(02),sign_each_row_i(02),out_min_1_new_i(02),out_min_2_new_i(02),index_min_new_i(02),sign_value_new_i(02),sign_each_row_new_i(02),L_matrix_new_02);
new_min_value_03:new_min_value port map(clk_internal,clr_1,reset,L_matrix_03,col_index_nonzero_03,col_L_nonzero_03,length_row_i,out_min_1_i(03),out_min_2_i(03),index_min_i(03),sign_value_i(03),sign_each_row_i(03),out_min_1_new_i(03),out_min_2_new_i(03),index_min_new_i(03),sign_value_new_i(03),sign_each_row_new_i(03),L_matrix_new_03);
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process(clk_internal,clr_2)
variable ii:integer range 0 to 7;
variable stop_internal:bit;
begin
if clr_2='0' then
stop_internal:='1';
ii:=0;
clr_out<='0';
else
if (clk_internal 'event and clk_internal='1' )and stop_internal='1' then
if ii=length_row_i-1 then
ii:=0;--i<=7;
stop_internal:='0';
clr_out<='0';
else
ii:=ii+1;
i<=ii;clr_out<='1';
L_LLR(add_01(i))<=L_matrix_new_01(i);
L_LLR(add_02(i))<=L_matrix_new_02(i);
L_LLR(add_03(i))<=L_matrix_new_03(i);
end if;
end if;
end if;
end process;
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process(clk_internal,clr_1)
variable iii,s:integer range 0 to 100;
variable i1:integer range 1 to 13;
variable stop_internal:bit:='1';
variable start:bit;
--variable jj:integer range 1 to 1000000000;
begin
if reset ='1' then
iii:=0;--L_LLR<=(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0);
--
else
if (clk_internal 'event and clk_internal='1' ) then
if stop_internal ='1' then
if iii=100 then
start:='1';
iii:=1;
i1:=i1+1;
else
iii:=iii+1;
start:='0';
end if;
if iii=1 then
clr_i<='1';
else
clr_i<='0';
end if;
if iii=1 and i1/=13 then
ii<=i1;
out_min_1_i<=out_min_1(i1);
out_min_2_i<=out_min_2(i1);
index_min_i<=index_min(i1);
sign_value_i<=sign_value(i1);
sign_each_row_i<=sign_each_row(i1);
col_each_rowblock_i<=col_each_rowblock(i1);
H_i<=H(i1);
length_row_i<=length_row(i1);
out_min_1_new(ii)<=out_min_1_new_i;
out_min_2_new(ii)<=out_min_2_new_i;
index_min_new(ii)<=index_min_new_i;
sign_value_new(ii)<=sign_value_new_i;
sign_each_row_new(ii)<=sign_each_row_new_i;
col_index_nonzero(ii)<=col_index_nonzero_i;
else
null;
end if;
if i1=13 then
stop_internal:='0';
else
stop_internal:='1';
end if;
else
out_min_1_new(12)<=out_min_1_new_i;
out_min_2_new(12)<=out_min_2_new_i;
index_min_new(12)<=index_min_new_i;
sign_value_new(12)<=sign_value_new_i;
sign_each_row_new(12)<=sign_each_row_new_i;
-- col_index_nonzero(12)<=col_index_nonzero_i;
end if;
else
--if clr_out='1' then
--end if;
--clr_i<='0';
end if;
end if;
end process;
------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------------------------------------------
length_row<=(7,8,8,7,7,8,7,7,8,7,7,7);
col_each_rowblock<=(
(1, 1, 1,1,1,1, 1),
(1, 1, 1,1,1,1, 1),
(1, 1, 1,1,1,1, 1),
(1, 1, 1,1,1,1, 1),
(1, 1, 1,1,1,1, 1),
(1, 1, 1,1,1,1, 1),
(1, 1, 1,1,1,1, 1),
(1, 1, 1,1,1,1, 1),
(1, 1, 1,1,1,1, 1),
(1, 1, 1,1,1,1, 1),
(1, 1, 1,1,1,1, 1),
(1, 1, 1,1,1,1, 1));
H<=(
(1, 1, 1,1,1,1, 1),
(1, 1, 1,1,1,1, 1),
(1, 1, 1,1,1,1, 1),
(1, 1, 1,1,1,1, 1),
(1, 1, 1,1,1,1, 1),
(1, 1, 1,1,1,1, 1),
(1, 1, 1,1,1,1, 1),
(1, 1, 1,1,1,1, 1),
(1, 1, 1,1,1,1, 1),
(1, 1, 1,1,1,1, 1),
(1, 1, 1,1,1,1, 1),
(1, 1, 1,1,1,1, 1));
end;