error in synthesis ISE 13.3

hello, how can I remove errors?(I use ISE 13.3)


ERROR:NgdBuild:455 - logical net
'Message_CN_VN_new_00/sign_value_new_12__2__1__1_OBUF' has multiple
driver(s):
ERROR:NgdBuild:462 - input pad net
'Message_CN_VN_new_00/sign_value_new_12__2__1__1_OBUF' drives multiple
buffers:
ERROR:NgdBuild:924 - input pad net
'Message_CN_VN_new_00/sign_value_new_12__2__1__1_OBUF' is driving non-buffer
primitives:
ERROR:NgdBuild:947 - input pad net
'Message_CN_VN_new_00/sign_value_new_12__2__1__1_OBUF' is driving non-input
buffer(s):

ERROR:NgdBuild:809 - output pad net
'Message_CN_VN_new_00/new_min_value_01/a0<6>' has an illegal load:
ERROR:NgdBuild:809 - output pad net
'Message_CN_VN_new_00/new_min_value_01/a0<5>' has an illegal load:
ERROR:NgdBuild:809 - output pad net
'Message_CN_VN_new_00/new_min_value_01/a0<4>' has an illegal load:
ERROR:NgdBuild:809 - output pad net
'Message_CN_VN_new_00/new_min_value_01/a0<3>' has an illegal load:
ERROR:NgdBuild:809 - output pad net
'Message_CN_VN_new_00/new_min_value_01/a0<2>' has an illegal load:
ERROR:NgdBuild:809 - output pad net
'Message_CN_VN_new_00/new_min_value_01/a0<1>' has an illegal load:
ERROR:NgdBuild:809 - output pad net
'Message_CN_VN_new_00/new_min_value_01/a0<0>' has an illegal load:

Do you honestly expect us to wade through 4000 lines of errors and code? At least show us you're exerting a LITTLE effort.

The 'multiple buffer' error tells you that you've got two sources driving the same signal, that should be easy to find. Many of the subsequent errors are probably due to that error.

barry said:

Do you honestly expect us to wade through 4000 lines of errors and code? At least show us you're exerting a LITTLE effort.

Click to expand...

Heh, that and please just keep it in one thread. Thanks.

The 'multiple buffer' error tells you that you've got two sources driving the same signal, that should be easy to find. Many of the subsequent errors are probably due to that error.

Click to expand...

And as a more general piece of advice, you can often google those errors and find out what they mean:

"OBUF is driving non-bufferprimitives" ==> http://www.google.com/webhp?q=OBUF is driving non-bufferprimitives => http://forums.xilinx.com/t5/Archive...-same-direction-cannot-be-placed-in/td-p/9731 and a few others.

That, and if this is your first real design, start with something small and manageable. That way you can ramp up your error message interpretation $k1llz without getting overwhelmed by 349867234876 errors all at once.

I modify it.
I am new in vhdl,I dont know where is "sign_value_new_12__2__1__1_OBUF'" in the program .

- - - Updated - - -

thank you ,what is the meaning of _12__2__1__1_ in sign_value_new?

guessing "sign_value_new" is one of your signals. The rest of the name is made up on the spot by XST during synthesis. OBUF means it's an output buffer, so presumably an output on your top level module.

ROFL!!! So do an updated question about sign_value_new, and remove the code that gave the question context. Yeah, that'll work.

I remove it bacause I think it dont need the code or the code dont any help to solve question,

Fair enough. Anyways I suggest you read the documentation on for example OBUFs, that is "xilinx OBUF primitive" in google for the lazy. And the library user guide for the less than lazy. That way you'll see what you can and cannot connect to an OBUF. Oh and you get OBUFs on the output of your toplevel design because that's what the default ISE options tell it to do.

I suggest you go over the options in ISE to get a rough idea of what's there.

Another thing to look at: there is an option to have XST add OBUFs automatically. If you add them in your code , you'll get an error.

That's what I just said. Well, or tried to say anyway.

mrflibble said:

.... Oh and you get OBUFs on the output of your toplevel design because that's what the default ISE options tell it to do.

Click to expand...

And indeed adding OBUFs by hand as well would indeed cause problems. But I doubt the OP is adding OBUF primitives since this is his first vhdl project.

You can find the option in ISE like so:

Synthesize - XST => Process Properties => Xilinx Specific Options => -iobuf (Add I/O Buffer)

That's enabled by default.