Error in Synthesis in Xilinx ISE 14.7 (INTERNAL_ERROR)

Hi,

I recently complied a VHDL program for a 4-bit adder/subtractor using Xilinx ISE 14.7 and suddenly got the error message -

INTERNAL_ERROR:Xst:cmain.c:3464:1.56 -
Process will terminate.
For technical support on this issue, please open a WebCase with this project attached at https://www.xilinx.com/support.

I also got warning messages about a missing .stx file for the project.

I could not find anything wrong with the VHDL code.

I went to google and found the answer at the following URL -
**broken link removed**

What the above link says is -
From the main menu in Xilinx ISE 14.7 -
Project -> Cleanup Project Files…
Press 'ok'.

This made the error message go away and I could synthesize my VHDL code and produce a .BIT file. I also tested the design for the 4-bit adder/subtractor on the NEXYS-2 FPGA board.

Anyone else experience this with Xilinx ISE ?
If so I hope the above helps.

There is also a similar thread on this matter at -
https://www.edaboard.com/threads/260103/

blakes7 said:

INTERNAL_ERROR:Xst:cmain.c:3464:1.56 -
Process will terminate.
For technical support on this issue, please open a WebCase with this project attached at https://www.xilinx.com/support.
...
Anyone else experience this with Xilinx ISE ?

Click to expand...

Seen it far too many times. I don't see it very often anymore as I regularly delete my entire build directory every time I rerun a build. Since I normally script my builds, it's pretty easy to have the script wipe out all the files and rebuild fresh from the source files. With Vivado it's even easy to script the BD generation and all the IP cores from the XCI files.