[SOLVED] Error in SV module compilation

[ashishk]

Hi,

My TB is in VHD and I created a bfm(mdio_phy) in verilog as follows:
*************************************
interface mdio_if;
logic clk;
logic nRst;
logic mdio;
endinterface:mdio_if


module mdio_phy (
inout mdio,
input mdclk,
input nReset
);

****************
code.......
**************
//Interface instance
mdio_if ports_if (
.clk(mdclk),
.nRst(nReset),
.mdio(mdio)
);


endmodule

During compilation I am getting an error saying that clk, nRST and mdio are not defined in interface mdio_if. Please tell me what is wrong.

Thanks,
Ashish

 

[dave_59]

There are no ports in your interface, so there are no ports to connect when you instantiate the interface

interface mdio_if;
logic clk;
logic nRst;
wire mdio; // needs to be a wire to be connected to an inout port.
endinterface:mdio_if

//Interface instance
mdio_if ports_if (); // empty port list
//module instance
mdio_phy phy(.mdclk(ports_if.clk),.nReset(ports_if.nRst),.mdio(ports_if.mdio) );  // hierarchical references to signals inside the interface.

Alternatively, you could change your interface definition to have ports

interface mdio_if (
output logic clk,
output logic nRst,
input wire mdio );
endinterface:mdio_if

And then the interface instantiation you wrote would work. In both case, the connections to the interface are the same as if the interface was defined as a module.

 

[ashishk]

Hi Dave,

Second solution seems to have syntax error and I am getting error for that.
As I told you that my top TB is in VHDL so I don't think taking an instance of interface at top will work. That's why I was taking intance of interface inside mdio_phy module and from there I was doind port map to the ports coming through mdio_phy module and from here only I will pass this interface handle to other classes.

Regards,
Ashish

- - - Updated - - -

Hi Dave,

Second solution was perfect. I had to add ; after the brace and it worked. Thanks a lot.

Regards,
Ashish