Error in subtraction with 2's comp method

[kooheyakhi]

Consider 3_bit wide number system. Then range is between -4 to +3. We
are going to perform subtraction +3-(-4). We know that result is +7
that does not fit range. So something is wrong. We expect that
hardware will alarm there is mistake because of overflow. Hardware
uses XOR operation between carry to/from MSB. If XOR=1 there is
overflow. In my example hardware cannot detect overflow. Where is the
mistake?? +3 and -4 are true operands since they are in the range.
Hardware only gets 2's complement of subtrahend when operation is
subtraction and add it to the minuend. Finally XOR determines if there
is overflow or not! In Moris Manos's Computer Architecture book there
is a ripple adder that performs proper operation based on control
mode. When we need to do subtraction, Subtrahend passes through XOR
gates and a '1' bit enters LSB of ripple adder to realize 2's
complement. I think problem arises when hardware negates -4. because
its 2's complement yields again -4, not +4. In fact +4 is not in the
range. But hardware how can find that subtrahend is -4.

 

[KlausST]

Hi,

So something is wrong.

Please tell us what is wrong. Tell us the result and tell us carry.

We expect that hardware will alarm there is mistake because of overflow.

Show us your hardware, schematic, code, or whatever you have.

Hardware only gets 2's complement of subtrahend when operation is
subtraction and add it to the minuend.

Did you do the calculation step by step on your own? With a pencil and paper?
What is the result of "2's complement of subtrahend"?
What is the result of the "add"?

I think problem arises when hardware negates -4. because
its 2's complement yields again -4, not +4. In fact +4 is not in the
range. But hardware how can find that subtrahend is -4.

I agree. Thus will be the problem.
But who is the designer if the hardware? He should tell you how to handle it...and where the limitations of the adders are.
If you are the designer you have a couple of options:
* do true subtraction (not 2's complement and the add)
* don't allow the subtrahend to be '-4'
* use 4 bits arithmetics (3 bits plus sign)
* correct your hardware to care for "2's complement overflow"
* or find another solution..

Klaus

 

[kaz1]

The rules are there for the designer:
to add/subtract n bits with n bits: result needs n+1 bits
to multiply n bits x m bits: results needs n+m bits

 

[ads-ee]

To perform subtraction in 2's complement the subtrahend of -4 is in binary:
100
011 - invert
100 - +1 (hmm result is -4)
011 - minuend
111 - add 2s comp subtrahend and minuend (no carry)

The subtrahend of the subtraction is adding a +4 which can't even be represented in the range of values allowed in the 3-bit vector. Of course computing overflow will result in incorrect results.

If we restrict the subtrahend to -3
101 - -3
010 - invert
011 - +1
011 - minuend
110 - add minuend to 2s comp subtrahend (we have a carry, so overflow occurred)

If instead we use 4-bits
3 - -4
1100
0011 - invert
0100 - +1 (2s comp of -4)
0011 - add minuend and subtrahend
0111 - +7 (no carry, correct result)