error in my VHDL Code (microprocessor 16 bits)

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bob2987

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Hi all !

I have some problems in my code.

I created different parts of microprocessor (PC,MAR,Memory ...) When i assembled the all modules i have few problems in the simulation. I haven't the same results with the complete design and with the simulation of one module (PC for example). How i can post my code because it's about 200 lines ...
 
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If you are facing to some problem concerning to an eventual size limit for text insertion at body post, can instead attach it as a compacted file.



+++
 

Hi all !

This is my code. When i checked MUX_MAR.vhd and MUX_MAR_tb.vhd it works but when i assembly all the modules in micrprocessor.vhd it doesn't work especially in module MUX_MAR. I haven't the same comportement Perhaps i did mistakes with the names of signals.

Thank you for your help.
 

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Microprocessor.vhd has no outputs. Hence it will synthesise to nothing, and is useless code.
 

Is it a problem if a module have no output? I have to create an output? But I don't know which output.
 

With no outputs, your design technically does nothing, so the synthesisor will just remove everything.
 

TrickyDicky said:
With no outputs, your design technically does nothing, so the synthesisor will just remove everything.
Click to expand...

Thank you. I add an output (output_memory ) but unfortunately it changes nothing. How can i do ?
 

I think there is a basic misunderstanding. What exactly are you trying to do with this design? what is the goal? Are the problems with simulation or synthesis?

Just adding any old output will not just make it work. You need the correct output - ie. the output of your system - the goal you are trying to acheive.
 


I have problem in the simulation. My goal is to see if my microprocessor works, i check if the adress memeory is read by the memory but unfortunately it is not the correct adress in input of the memory.

- - - Updated - - -

I have also this kind of warning

WARNING: Simulation object /microprocessor_tb/UUT/B_memory was not found in the design.
WARNING: Simulation object /microprocessor_tb/UUT/B_memory was not found in the design.
WARNING: Simulation object /PC_tb/sbranch was not found in the design.
WARNING: Simulation object /PC_tb/sincr was not found in the design.
WARNING: Simulation object /PC_tb/sld was not found in the design.
WARNING: Simulation object /PC_tb/sRAZ was not found in the design.
WARNING: Simulation object /PC_tb/sclk was not found in the design.
WARNING: Simulation object /PC_tb/sQ was not found in the design.
WARNING: Simulation object /microprocessor_tb/UUT/Z5/etat_present was not found in the design.
WARNING: Simulation object /MAR_tb/sD was not found in the design.
WARNING: Simulation object /MAR_tb/sld was not found in the design.
WARNING: Simulation object /MAR_tb/sRAZ was not found in the design.
WARNING: Simulation object /MAR_tb/sclk was not found in the design.
WARNING: Simulation object /MAR_tb/sQ was not found in the design.
WARNING: Simulation object /microprocessor_tb/UUT/Z3/Q was not found in the design.
WARNING: Simulation object /microprocessor_tb/UUT/Z3/temp was not found in the design.
WARNING: Simulation object /microprocessor_tb/UUT/Z3/O1/RAZ was not found in the design.
WARNING: Simulation object /microprocessor_tb/UUT/Z3/O1/ld was not found in the design.
WARNING: Simulation object /microprocessor_tb/UUT/Z3/O1/clk was not found in the design.
WARNING: Simulation object /microprocessor_tb/UUT/Z3/O1/D was not found in the design.
WARNING: Simulation object /microprocessor_tb/UUT/Z3/O1/Q was not found in the design.
Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).


I don't understand this warning.
 

The first set of warnings occur when the object you have in the waveform script dont exist in the design
the final one is a warning about arithmatic with non-0/1 values. Usually it occurs from uninitialised signals. These can be turned off in the simulation settings.
 

Thank you, so it's not a big problem with the warnings. I check the RTL schematic , the connections with signals are correct.
 

This is my MAR.vhd

Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity MAR is
    Port ( ld : in STD_LOGIC;
           RAZ : in STD_LOGIC;
           clk : in STD_LOGIC;
           D : in STD_LOGIC_VECTOR (12 downto 0);
           Q : out STD_LOGIC_VECTOR (12 downto 0));
end MAR;
 
architecture Behavioral of MAR is
begin
process(RAZ,clk)
begin
if (RAZ ='0') then
Q <= "0000000000000";
    elsif (clk'event and clk ='1') then
    if (ld='1') then
    Q <= D;
    else Q <= "ZZZZZZZZZZZZZ";
    end if;
end if;
end process;
end Behavioral;



I don't know why in the simulation, my input D is read when the reset = '0'. So i have all the time Q = "0000000000000"

I try to change reset = '1' it works but i would like that it works with '0'.

Thank you.
 
Last edited by a moderator:

TrickyDicky said:
I assume those problems are like that because of your testing stimulus.
Click to expand...

Ok thank you but it's strange that i have a good comportement when the module MAR is independant and a bad comportement when it is assembly with the same stimulus.
 

Well, thats the advantage of the simulator - you can view all internal signals so you can trace the problem and debug it..
 

TrickyDicky said:
Well, thats the advantage of the simulator - you can view all internal signals so you can trace the problem and debug it..
Click to expand...

Sure TrickyDicky , it's an advantage. Now, i have to fix my problem of the module MAR.vhd. If anyone find an error in my code.

Thank you.
 

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