mohamis288
Full Member level 3
Hello,
I am compiling testbench file in modelsim. My Testbench Verilog code is here:
But this error will be shown:
'Address_me' has been defined once. What does it say?
Best regard
I am compiling testbench file in modelsim. My Testbench Verilog code is here:
Code:
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Module Name: FIR_TB
module FIR_TestBench;
parameter N = 8;
reg clk, reset;
reg [N-1:0] my_data_in;
wire [N-1:0] my_data_out;
FIR_Filter inst0(clk, reset, my_data_in, my_data_out);
// input sine wave data
initial
$readmemb("signal.data", RAMM);
// Create the RAM
reg [N-1:0] RAMM [31:0];
// create a clock
initial
clk = 0;
always
#10 clk = ~ clk;
// Read RAMM data and give to design
always@(posedge clk)
my_data_in <= RAMM[Address_me];
// Address_me counter
reg [4:0] Address_me;
initial
Address_me = 1;
always@(posedge clk)
begin
if (Address_me == 31)
Address_me = 0;
else
Address_me = Address_me + 1;
end
endmoduleBut this error will be shown:
Code:
** Error: /home/user1/CAD/final/final/FIR_TestBench.v(33): (vlog-2730) Undefined variable: 'Address_me'.
** Error (suppressible): /home/user1/CAD/final/final/FIR_TestBench.v(36): (vlog-2388) 'Address_me' already declared in this scope (FIR_TestBench) at /home/user1/CAD/final/final/FIR_TestBench.v(33).'Address_me' has been defined once. What does it say?
Best regard