Error in generating netlist according to Xilinx EDK tutorial

[raylay]

Xilinx EDK help

I follow the EDK6.1 tutor.when i generate netlist, the error come out,
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(Console Log)
Project Opened.
Command bash -c "cd /xygdrive/e/temp/XilinxReferenceSystems/plb_ssp3_v1_00_a/; make -f system.make netlist; exit;" Started...
*********************************************
Creating system netlist for hardware specification..
*********************************************
platgen -p xc2vp7fg456-6 -lang vhdl -st xst system.mhs
Release 6.1i - platgen EDK_G.12
Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved.
ERROR:MDT - Invalid target speed '-6'
ERROR:MDT - platgen failed with errors!
make: *** [implementation/system.ngc] Error 2Done.

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but I couldn't modify target speed option!

Thank you for your advise!