[SOLVED] error in creating Fifo core

[amin5659]

hi all.
when i want to create Fifo with ip core generator,i receive this error :

"D:\Xilinx\14.7\ISE_DS\ISE\coregen\repository\xilinx.com\generators\ise_proje
ct_generator_v1_0.tcl" line 355)ERROR:sim - Unable to evaluate Tcl file:
D:\Xilinx\14.7\ISE_DS\ISE\coregen\repository\xilinx.com\generators\ise_projec
t_generator_v1_0.tcl
ERROR:sim - Failed executing Tcl generator.
ERROR:sim - Failed to generate 'ff'. Failed executing Tcl generator.

Wrote CGP file for project 'ff'.
Core Generator create command failed.

i have cleaned up the project and also created the new project but this still happen.
the important thing is Ip core gen create Dcm core or divider core successfully .its problem is with mem cores...:shock::shock:

 

[ads-ee]

does the ise_project_generator_v1_0.tcl file even exist in the location specified?

 

[amin5659]

no. i couldn't find that file in location...

 

[ads-ee]

Well that kind of explains the error. Now why didn't it create the file...Is there any other warnings when running ip core generator?

 

[amin5659]

yes.it has 3 warning .
this is full massage :

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[I]INFO:HDLCompiler:1061 - Parsing VHDL file "D:/science/VHDL & FPGA/test/test/f.vhd" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Launching Design Summary/Report Viewer...
The IP Catalog has been reloaded.
INFO:sim:172 - Generating IP...
Resolving generics for 'we'...
Applying external generics to 'we'...
Delivering associated files for 'we'...
Delivering EJava files for 'we'...
Generating implementation netlist for 'we'...
INFO:sim - Pre-processing HDL files for 'we'...
[B]WARNING[/B]:sim - BlackBox generator run option '-ifmt' found multiple times. Only
   the first occurence is considered.
Running synthesis for 'we'
Running ngcbuild...
Writing VHO instantiation template for 'we'...
Writing VHDL behavioral simulation model for 'we'...
[B]WARNING[/B]:sim - Overwriting existing file D:/science/VHDL &
   FPGA/test/test/ipcore_dir/tmp/_cg/we/doc/fifo_generator_v9_3_vinfo.html with
   file from view xilinx_documentation
Delivered 3 files into directory D:/science/VHDL &
FPGA/test/test/ipcore_dir/tmp/_cg/we
Delivered 1 file into directory D:/science/VHDL &
FPGA/test/test/ipcore_dir/tmp/_cg/we
Generating ASY schematic symbol...
INFO:sim:949 - Finished generation of ASY schematic symbol.
Generating SYM schematic symbol for 'we'...
Generating metadata file...
Generating ISE project file for 'we'...
[B]WARNING[/B]:coreutil - can't create directory "D:/science/VHDL D:science": not a
   directory
       while executing
   "file mkdir [file dirname $uniqueItem] "
       ("foreach" body line 3)
       invoked from within
   "foreach item [::xilinx::GeneratorUtils::recursiveGlob
   $wrongMessageDirectory] {
                     regsub $wrongMessageDirectory $item $correctMessageD..."
       (procedure "createIseProject" line 284)
       invoked from within
   "createIseProject $componentInstanceID $envId"
       (procedure "main" line 29)
       invoked from within
   "main $argc $argv"
       invoked from within
   "return [main $argc $argv]"
       (file
   "D:\Xilinx\14.7\ISE_DS\ISE\coregen\repository\xilinx.com\generators\ise_proje
   ct_generator_v1_0.tcl" line 355)ERROR:sim - Unable to evaluate Tcl file:
   D:\Xilinx\14.7\ISE_DS\ISE\coregen\repository\xilinx.com\generators\ise_projec
   t_generator_v1_0.tcl
ERROR:sim - Failed executing Tcl generator.
ERROR:sim - Failed to generate 'we'.  Failed executing Tcl generator.
 
Wrote CGP file for project 'we'.
Core Generator create command failed.[/I]

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[TrickyDicky]

change the path to remove all spaces - the tools are a bit dumb when it comes to whitespace in paths. use _ instead.

 

[amin5659]

wowwwwww :clap:
this has wasted my time for almost 3 days :|
every path I tried had space or - .
thanks

 

[TrickyDicky]

wowwwwww :clap:
this has wasted my time for almost 3 days :|
every path I tried had space or - .
thanks

Yup - I think this is one we've all learned the hard way. Just make a habit of using _ for everything