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error for my vhdl design

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gholamzadeh

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hi
i wrote a vhdl code for read and write from sd card,and i have a problem,this error deny me to synthesize this code in xilinx
i have 4 array(0 to 160) of std_logic_vector(7 downto 0)
ERROR:pack:18 - The design is too large for the given device and package.
ERROR: MAP failed

I do not know how little of its size
please help me
thanx
 

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