Error during LVS run (Cadence Virtuoso IC5033)

[jyothirmayeec]

Hello
I am working on cadence virtuoso IC5033. I am able to run DRC and get the extracted view of the layout.But when I am trying to run LVS i am getting error saying:

"*WARNING* Invalid LVS run directory.
/home/haritez/adelab/adelabic/LVS/layout/netlist is not valid.
You must initialize the LVS run
with a valid LVS run directory before you can probe."

I have checked the si.log file.It is giving a global error regarding the cell view,

" *WARNING* invalid cell view -- 0(unknown)
*WARNING* invalid cell view -- 0(unknown)
*WARNING* invalid cell view -- 0(unknown)
*WARNING* invalid cell view -- 0(unknown)
*WARNING* invalid cell view -- 0(unknown)
global error:
Cannot find switch master cell for instance M1 in cellView (inverter schematic) from viewlist 'lvs schematic gate_sch cmos_sch ' in library 'expt1'.
global error:
Cannot find switch master cell for instance M0 in cellView (inverter schematic) from viewlist 'lvs schematic gate_sch cmos_sch ' in library 'expt1'.
*WARNING* invalid cell view -- 0(unknown)
si: Netlist did not complete successfully.
Comparison program did not complete. Check the log".

i am struck here.plz help me to resolve this problem.

thanks
Jyothirmayee

MODERATOR ACTION: Moved from "About EDAboard.com" forum.

 

[eng_Semi]

cadence invalid lvs run directory

Try to send ur question in the Analog Layout forum to get more answers on ur question.

For ur problem try to corresctly write the path of the folder (in which the run will be saved) with ur hand.

 

[holddreams]

lvs schematic gate_sch cmos_sch

How do you run LVS?

Calibre?Drucula?Or else?

 

[Hughes]

cadence lvs

It seems that your schematic uses some gates without a schematic view. All the standard cells, inverters, nand gates, nor gates, etc., should have their schematic views.

 

[Teddy]

cadence global error

From the log you are showing I assume you are using DIVA LVS.

If so it seems like there is a issue with the viewlist used for LVS.
This should be defined in .simrc file like for example:
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; for transistor-level comparison for analog artist

lvsSchematicViewList = '( "auLvs" "schematic" "gate.sch" "cmos_sch" )
lvsLayoutViewList = '( "auLvs" "extracted" "schematic" "gate.sch" "cmos_sch")
lvsLayoutStopList = '( "auLvs" )
lvsSchematicStopList = '( "auLvs" )

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; force LVS to use the most current version of cellviews for comparison
lvsLayoutVersionName = nil
lvsSchematicVersionName = nil


Once you specify the list of views cadence will be able to go to correct one and you LVS will run.

Hope this helps!

Added after 27 seconds:

From the log you are showing I assume you are using DIVA LVS.

If so it seems like there is a issue with the viewlist used for LVS.
This should be defined in .simrc file like for example:
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; for transistor-level comparison for analog artist

lvsSchematicViewList = '( "auLvs" "schematic" "gate.sch" "cmos_sch" )
lvsLayoutViewList = '( "auLvs" "extracted" "schematic" "gate.sch" "cmos_sch")
lvsLayoutStopList = '( "auLvs" )
lvsSchematicStopList = '( "auLvs" )

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; force LVS to use the most current version of cellviews for comparison
lvsLayoutVersionName = nil
lvsSchematicVersionName = nil


Once you specify the list of views cadence will be able to go to correct one and you LVS will run.

Hope this helps!

 

[gszczesz]

lvs invalid directory cadence

By any chance are you using Polar Fab?

I've seen similar problems with certain PDK's. The initial problem was due to the OS it was installed on: namely when the skill code retrieves a directory/file list, the returned list is in different order then that the code that it was debugged on. Most skill code is debugged on OS's where the first two directories or files listed are "." and "..". Most programmers then assume a directory/file listing is ordered and they chop out the first two entries. On OS's where the order is different, it results in valid files/directories not being included and thus poorly performing code. Polar's PDK has such a problem when they are searching for skill files to include.

This problem has also been observed on version 5.0.33 that uses "alternative" licensing schemes. To fix it, you will have to move a more "traditional" licensing arrangement.

 

[gszczesz]

lvs run directory

I've asked around work for people who've seen this problem, and we do have a laptop here running Cadence 5.0.33.500.3.27 and another companies PDK that exhibits this problem. The funny part is that the exact same Cadence/PDK combination on other Linux machines work fine (we actually tarred the directories over).

In any case, we traced the problem to the following: when running LVS, the "Begin netlist at: ... " statement in the log file happens BEFORE the PDK's skill code is loaded. All the settings in si.env file are wrong, including the view name lists and stop lists. When we change the si.env file to represent the correct settings, other problems appear later on. On the working machines, the skill code is loaded first, and then the netlist is performed.

I hope this gives someone a clue as to what is different/wrong between the two machines. We contacted the PDK's EDA group and they've never seen it before, and Cadence has yet to get back to us.

Greg