error code in vhdl. Can anybody help me? plz

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azwaa

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Hi guys!

i have problems with my vhdl code.

can you help me plz

This is the code:
Code: 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;


entity correla is

port (
         clk : in    std_logic ;
         rst : in    std_logic  ;
         data: in    std_logic_vector(11 downto 0)  ;
       

         code: in    std_logic_vector(15 downto 0 )  ;
        
         Q   :out    std_logic_vector(17 downto 0) )  ;
end entity ;

architecture arch of correla  is 
       type RAM is array (0 to 3) of std_logic_vector(3 downto 0) ;
     
       type ram16 is array (0 to 3) of signed(15 downto 0) ;

        signal CD    : RAM;
        signal temp: ram16;
     
        
        

        signal sum   :signed (16 downto 0) ;
        signal AB    :signed (17 downto 0) ;
        
begin
  
    CD(0) <= code(15 downto 12);
    CD(1) <= code(11 downto 8);
    CD(2) <= code(7 downto 4);
    CD(3) <= code(3 downto 0);    
     étalement:process(clk,rst)
           
        begin 
                  if(rst='1') then 
                     Q  <=(others=>'0');
                     
                     temp(0)<=x"0000";
                     temp(1)<=x"0000";
                     temp(2)<=x"0000";
                     temp(3)<=x"0000";
                      
                   
                   else 
                        if(clk'event and clk ='1') then 
                            
                               
                                     
                                      for i in 0 to 3 loop 
                                    temp(i) <= signed(data)*signed(CD(i));
                                      end loop ;
                                      
                                      sum(0)<= temp(0)+temp(1) ;
                                      sum(1)<= temp(2)+temp(3) ;
                                      
                                         AB<=sum(0)+sum(1) ;
                                         
                                         Q<=std_logic_vector(AB) ;
                                         
--                                

                                  
                                            
                                  
                             end if ;
                     end if ;  
                                     
                        
                       
            end process ;
 end architecture ;

error : Error (10327): VHDL error at correla.vhd(60): can't determine definition of operator ""+"" -- found 0 possible definitions
Code: 
                                      sum(0)<= temp(0)+temp(1) ;

Thank you in advance for your reponse !!:-(
 

I think you should declare this package too...
Code: 
use ieee.math_real.all ;
 

like this :

Code: 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;


entity correla is

port (
         clk : in    std_logic ;
         rst : in    std_logic  ;
         data: in    std_logic_vector(11 downto 0)  ;
       

         code: in    std_logic_vector(15 downto 0 )  ;
        
         Q   :out    std_logic_vector(17 downto 0) )  ;
end entity ;

architecture arch of correla  is 
       type RAM is array (0 to 3) of std_logic_vector(3 downto 0) ;
     
       type ram16 is array (0 to 3) of signed(15 downto 0) ;
        type Rom is array (0 to 3) of signed(16 downto 0) ;

        signal CD    : RAM;
        signal temp: ram16;
        signal sum :Rom ;
     
        
        

       
        signal AB    :signed (17 downto 0) ;
        
begin
  
    CD(0) <= code(15 downto 12);
    CD(1) <= code(11 downto 8);
    CD(2) <= code(7 downto 4);
    CD(3) <= code(3 downto 0);    
     etalement:process(clk,rst)
           
        begin 
                  if(rst='1') then 
                     Q  <=(others=>'0');
                     
                     temp(0)<=x"0000";
                     temp(1)<=x"0000";
                     temp(2)<=x"0000";
                     temp(3)<=x"0000";
                     sum(0)<="00000000000000000";
                     sum(1)<="00000000000000000";
                      
                   
                   else 
                        if(clk'event and clk ='1') then 
                            
                               
                                     
                                      for i in 0 to 3 loop 
                                    temp(i) <= signed(data)*signed(CD(i));
                                      end loop ;
                                      
                                      sum(0)<= temp(0)+temp(1) ;
                                      sum(1)<= temp(2)+temp(3) ;
                                      
                                         AB<=sum(0)+sum(1) ;
                                         
                                         Q<=std_logic_vector(AB) ;
                                         
--                                

                                  
                                            
                                  
                             end if ;
                     end if ;  
                                     
                        
                       
            end process ;
 end architecture ;

error : Error (10344): : expression has 16 elements, but must have 17 elements

Code: 
                                      sum(0)<= temp(0)+temp(1) ;

thanks a lot
 

The code looks nearly correct, but I didn't check for functionality.

A few corrections necessary:
Code: 
signal sum0   :signed (16 downto 0) ;
signal sum1   :signed (16 downto 0) ;
...
sum0<= resize(temp(0),17)+temp(1) ;
sum1<= resize(temp(2),17)+temp(3) ;
AB<=resize(sum0,18)+sum1 ;
 

thank you my friend !

but can you give me more information about :

Code: 
resize(temp(0),17)+temp(1)

why exactly did you choose 17 for temp(0) not temp(1) !!?
 

Hi,
What FVM wrote is a resize function which will resize temp(0) which is 16 bit to 17 bit,

Following is the definition of resize function -

function RESIZE (ARG: SIGNED; NEW_SIZE: NATURAL) return SIGNED;
attribute builtin_subprogram of
RESIZE[SIGNED, NATURAL return SIGNED]: function is
"numstd_resize_sns";
-- Result subtype: SIGNED(NEW_SIZE-1 downto 0)
-- Result: Resizes the SIGNED vector ARG to the specified size.
-- To create a larger vector, the new [leftmost] bit positions
-- are filled with the sign bit (ARG'LEFT). When truncating,
-- the sign bit is retained along with the rightmost part.
 

azwaa said:
thank you my friend !

but can you give me more information about :

Code: 
resize(temp(0),17)+temp(1)

why exactly did you choose 17 for temp(0) not temp(1) !!?
Click to expand...

Because the the "+" function ensures all inputs are the same length before adding. So temp(1) is also extended to 17 bits.
 

TrickyDicky said:
Because the the "+" function ensures all inputs are the same length before adding. So temp(1) is also extended to 17 bits.
Click to expand...


Thank you :wink:


When I made the simulation :

Normally, the results will be : 1 1 -1 1 -1 -1 1 -1 1 1 -1 1(Multiplication between data and code)

Thank you in advance for your reponse
 

Attachments

  • error.PNG
    11.9 KB · Views: 91

As said, I didn't check the code serves a reasonable purpose. You have posted so many functionally different VHDL codes claimed to solve the same problem that I gave up to figure out what they are exactly doing.

I suggest to watch all intermediate signals in the simulation to understand how the result is generated,
 

Why don't you write down an example with input, expected intermediate results and output data? You can use it also to check the calculation steps in simulation yourself.

Presently I don't even understand the presentation of simulation data. Why do you split Q into 3 decimal numbers instead of displaying it binary?
 



Here is the schema what I did :




Thanks a lot :sad:
 

I have seen the diagram before, it's a bit vague. I appreciate an example with data values.
 

Hi!

plz Do you have any idea about Desetalement of spectre in VHDL ?!

Thank you in advance for your reponse
 

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