TH22
Newbie
Hello,
I have a question about synthesis in Design Vision.
After synthesis the VHDL source code in Design Vision I got the following error:
How can I fix the issue?
Thanks in advance.
I have a question about synthesis in Design Vision.
After synthesis the VHDL source code in Design Vision I got the following error:
"Error: Value for list 'source_objects' must have 1 elements. (CMD-036)"
How can I fix the issue?
Thanks in advance.