Error (10500): VHDL syntax error at near text "enable"; expectexpecting "begin", or

[wan khusairi]

Error (10500): VHDL syntax error at near text "enable"; expectexpecting "begin", or

hello im still new in thie VHDL and have very liitle bit programming skill. i have created a program that read movement from a PIr sensor and i would like the output of is to be maintained in minutes..here i attaced my program but it seem that error Error (10500): VHDL syntax error at AcounterGpio2.vhd(29) near text "enable"; expecting "begin", or a declaration statement existed and i dont know how to repair it. how can i eliminated the error. herewith is the code that i developed. really need your help for this program..


how does i program my counter so that the output will be maintained in minutes..tq in advance

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;

entity AcounterGpio2 is

port( PIRin : in std_logic;
clk : in std_logic;
reset : in std_logic;
PIRout : out std_logic;
q : out std_logic);

end AcounterGpio2 ;

architecture bufferwithGpio_arc of AcounterGpio2 is
signal cnt,enable: std_logic;

begin
process(PIRin)
begin
if PIRin = '1' then
PIRout <= PIRin ;
else PIRout <= '0';
end if;
end process;

counterrocess (clk)
enable <= PIRout;
begin
if (rising_edge(clk)) then
if reset = '1' then
cnt := 0;-- Reset the counter to 0
elsif enable = '1' then
cnt := cnt + 1;-- Increment the counter if counting is enabled
end if;
end if;
-- Output the current count

end process counter;
q <= cnt;
end bufferwithGpio_arc;

 

[TrickyDicky]

Re: Error (10500): VHDL syntax error at near text "enable"; expectexpecting "begin"

You cannot put signal assignments before the "begin" of a process.

Also - := is for assigning variables, not signals.

 

[axcdd]

Re: Error (10500): VHDL syntax error at near text "enable"; expectexpecting "begin"

There is also no possibility to read from output port in its architecture (PIRout : out std_logic. You can change it to inout port and do it (highly not recommended) or add another internal signal to handle this.

simple example of how u can handle this

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;

entity AcounterGpio2 is

  port ( 
    PIRin : in std_logic;
    CLK	 : in std_logic;
    RESET	 : in std_logic;
    PIRout : out std_logic
  );
end entity AcounterGpio2 ;

architecture bufferwithGpio_arc of AcounterGpio2 is
  
  --! your val to be counted
  constant END_VAL : integer :=100;
  
begin 
  
  counter:process(clk)
  variable cnt : integer :=0;
  begin
    if RISING_EDGE(CLK) then
      if RESET = '1' then
        cnt := END_VAL;-- Reset the counter to END_VAL
      elsif PIRin = '1' then
        cnt := 0;
        PIRout <='1';
      --! start counting to END_VAL 
      elsif cnt < END_VAL then
        cnt := cnt + 1;-- Increment the counter if counting is enabled
        PIRout <= '1';
      else
        cnt := END_VAL;
        PIRout <='0';
      end if;
    end if;	
-- Output the current count
end process counter;


end bufferwithGpio_arc;

If u want to maitance output for known time u just have to convert that time to clock ticks i.e: 1 minute when your clock is 1 Mhz req. counter that will count to 10^6, so in my simple code END_VAL shoudl be 1_000_000;

 

[TrickyDicky]

Re: Error (10500): VHDL syntax error at near text "enable"; expectexpecting "begin"

There is also no possibility to read from output port in its architecture (PIRout : out std_logic.

It is ok with VHDL 2008

You can change it to inout port and do it (highly not recommended) or add another internal signal to handle this.

Never ever do this, unless you're building a tri state bus.

simple example of how u can handle this

And also want to declare the counter like this, to prevent it creating a 32 bit integer.

  variable cnt : integer range 0 to 2**7-1 :=0;  --only implements 7 bits

 

[lucbra]

Re: Error (10500): VHDL syntax error at near text "enable"; expectexpecting "begin"

There were actually only 2 minor problems in the original code :
the line

enable <= PIRout;

should be moved to after the begin

and either you define cnt as a variable in the process (as suggested before) or you make cnt a signal (like you did), but then all the assignments should be changed to treat cnt as a signal:

cnt <= 0;-- Reset the counter to 0
...
cnt <= cnt + 1;-- Increment the counter if counting is enabled
...

Also, I would never ever read back an output port - quite tricky IMHO. I prefer a temporary signal as placeholder for the output value and then assign this to the output port.

making a port inout (i.e. tristate) is ok only if that port is the top level of your system

 

[wan khusairi]

Re: Error (10500): VHDL syntax error at near text "enable"; expectexpecting "begin"

how can i create a temporary signal as placehold for the output value and then assign it to the output port.. when should i use signal or variable and what is the difference between them.

for axcdd i have try running the program that you have editted and no error was found but when i try start to do pin assignment nothing happen..bye the way i just use 50Mhz clock as the clk and also the switch sw0 as it reset..have i done any mistake on using the clk or the switch as my rest button.

 

[TrickyDicky]

Re: Error (10500): VHDL syntax error at near text "enable"; expectexpecting "begin"

A signal is updated whenever the process that is assigned in suspends (eg hits a wait statement or finishes when it has been triggered by a signal in the senstivity list).
A variable is updated immediatly.

If you dont know the difference, then you should always stick with signal until you understand VHDL better. you're less likely to have problems.

 

[lucbra]

Re: Error (10500): VHDL syntax error at near text "enable"; expectexpecting "begin"

you're defining a temporary signal just the same as any other signal. To show the usage:

entity blabla
   port (
      in_data : in std_logic;
      out_data : out std_logic
   );
end entity blabla;

architecture ...

signal mysignal, another_signal : std_logic;

begin

process (...)
begin
   if ...
      another_signal <= '0';
   elsif rising_edge (..) then
      if mysignal = '1' then
         another_signal <=  ...
      else
         ....
      end if;
   end if;
end process;

process ...
begin
   if ..
      mysignal <= '0';
   elsif rising_edge ...
       mysignal <= '1';
   end if;
end process;

out_data <= mysignal;

end architecture ...;