Equation to show the relation between Vds(saturation) and W/L

[Blackuni]

Hi All,

Is thr any equation to show the relation between Vds(saturation) and W/L.

I like to hve a graph for this so that i can use it as a one more design variable while using Gm/Id method.

Please help me with your comments. I got struck up into this for Quiet some time now

Thanks,

 

[jiesteve]

Re: Vds and W/L

Well, the long channel equation for Vdsat is:

Vdsat = SQRT( 2 Id / k` (W/L) )

 

[Blackuni]

Re: Vds and W/L

hi,

Thanks, Its not much helpful in my case. Is there any other way?

Thanks,

 

[lavitaebelle]

Re: Vds and W/L

Use the same eqn in different ways,
Id=k/2(Vdsat)^2
gm=k(Vdsat)
gm/Id=Vdsat/2

Dont know what exactly you want.

 

[Blackuni]

Re: Vds and W/L

hi lavitaebelle,

Thanks, Here is my requirement. I like have Vds as one more design constrain, becoz it determines the voltage headroom/swing. so i like to have its relation with w/l

hope its clear. Please let me know if not or misleading

thanks,

 

[hr_rezaee]

Vds and W/L

Hi
maybe this paper can help you
(see eq 13)

Behavioral Modeling of Opamp Gain and Dynamic Effects for Power Optimization of Delta-Sigma Modulators and Pipelined ADCs
Anas A. Hamoui, T. Alhajj, and M. Taherzadeh-Sani
ISLPED'06, October 4-6, 2006, Tegerrsee, Germany.

regards

 

[Blackuni]

Re: Vds and W/L

Hi hr_rezaee,

Thanks, Can you help me with tht eq. or the paper i m not able to get tht paper

thanks,

 

[lavitaebelle]

Re: Vds and W/L

I assume its the over drive voltage (Vgs-Vth) you want vs W/L. For a fixed bias current, the overdrive voltage is inversely proportional to the square root of W/L. For a fixed gm, overdrive voltage is inversely proportional to W/L. You need to fix something like current or gm to get a relation between the other two parameters.

 

[Blackuni]

Re: Vds and W/L

Hi,

I am not luking for the overdrive voltage vs W/L

I like 2 have an eq or relation for Vds(voltage across drain and source) vs W/L

i need this because vds determines the voltage headroom. This will be much helpful if MOS transistors r stacked

Thnks,

 

[lavitaebelle]

Re: Vds and W/L

Why would vds depend on W/L? Drain is a high impedance node. The Id-Vds relation is a second order one. Changing W/L will not affect Vds whatsover as long as transistor is in saturation. The drain node voltage is fixed independently and not through the current or W/L.

 

[Blackuni]

Re: Vds and W/L

Hi,

If I have couple of transistor staked 1 over other and both are in saturation then how the voltage at the interface point is determined?

I know in spice it is done by NR algorithm. but how 2 do manually.


Here is an example spice deck
******
vdd1 nr1 gnd 1
.global vdd gnd 0
.param wen=35u
m3 nr1 n3 n1 gnd cmosn w=wen l=2u
m4 n1 n2 gnd gnd cmosn w=wen l=2u m=1 geo=0
vtail n2 gnd 0.0
vup n3 gnd 0.7
*******

How i can arrive at node n1 voltage. I am able to see chnage in the node voltage by chaning the device W/L

 

[raduga_in]

Vds and W/L

I have a similar kind of question .. what should be the case of a
cascode pair, if we want to set the voltage headroom exactly
half of availble to both devices ?

 

[lavitaebelle]

Re: Vds and W/L

You will obviously see node n1 changing with W/L. Why? because of Vgs of top transistor and not because of vds of bottom transistor. The value at node n1 is determined by Vgs of M3. The current in the transistors is determined by Vgs of the bottom transistor M4.
Firstly how is there any current in the circuit since you have given 0 Volts to the gate of the bottom transistor? Next, assuming you give sufficient bias to the first device, make sure the gate of M3 is sufficiently high so that transistor M4 is in saturation.
For proper working of the whole cascode, gate of M4 must have Vth+Vov and gate of M3 must have bias of Vth'+2Vov. Here Vth'>Vth because of body effect and Vov is typically kept around 100-200 mV.

 

[Blackuni]

Re: Vds and W/L

Hi,

Its a typo. As i mentioned both devices are in saturation.

 

[hr_rezaee]

Re: Vds and W/L

I like have Vds as one more design constrain, becoz it determines the voltage headroom/swing. so i like to have its relation with w/l

Hi
ohh,
No, you must have Vov to determine swing nor VDS.
I thought that you want to caculate gain in full swing.
I'm sorry, that paper can't help you.
but you make a big mistake.
regards

 

[Blackuni]

Re: Vds and W/L

Hi hr_rezaee,

Please point me the mistake i m doing!

Here are the points i like to know

1. If i have two transistors stacked(as the example i pasted earlier) how the VDS of the m3 and m4 is arrived at? Because if i like to keep the node n1 at vdd/2 then how can i achive it? I am able to do that by iterative SPICE simulations But i believe there should be some sort of mathematical relation.


If the design headroom is 1v then 100mv difference is a great number.

Sorry for asking such a simple Question but i don't have an ans for this so upto me its tough Q

Thanks,

 

[Blackuni]

Re: Vds and W/L

Hi,

Any comments!!

thanks,

 

[du_hast]

Re: Vds and W/L

Do you remember the inversor cell? Two transistors conected as your example, but with equal voltage at the gate. The same approach can be applied to your case and obviously there will be an expression of Vd for m4, and you can get it for a level 2 transistor model:
I=.5KW/L(Vgs-Vt)^2(1+lambda*Vds)

Both transistors have the same current, so you can replace I with the equation of the other transistor, then equate and solve for Vds.

Well you will have an expression with this, but the expression will be valid as level 2 model is, so if you are working with short chanels you will need other transistor model.

If this can help you don't forget the help button....

 

[Blackuni]

Re: Vds and W/L

Hi,

I tired u r suggestion earlier it works for low level models and not good for short channel as they r many variable parameters in the equation.

Is thr any alternate?

is it not at all necessary to wrry abt this?

Thanks,

 

[hr_rezaee]

Re: Vds and W/L

Hi hr_rezaee,

Please point me the mistake i m doing!

Here are the points i like to know

1. If i have two transistors stacked(as the example i pasted earlier) how the VDS of the m3 and m4 is arrived at? Because if i like to keep the node n1 at vdd/2 then how can i achive it? I am able to do that by iterative SPICE simulations But i believe there should be some sort of mathematical relation.

If the design headroom is 1v then 100mv difference is a great number.

Sorry for asking such a simple Question but i don't have an ans for this so upto me its tough Q

Thanks,

Hi
Pleaes give the link of your earlier post!!!
If you want to know how DC voltage of output node is set, read bellow:
in single ended opamps:
really feedback can set it.
in fully diff. opamps:
comon mode feedback.

so for your design you must know the DC or common mode of output node(s).
(or you must specify it.)

if yu have problem in design of Vds of transistors and bias volages see example 9.5 of Razavi's IC design book (page 299).
hope I could help you.
regards