EOC SOC in pipelined ADC

[anadigi]

I hav used Pipeliened architecture (2.5b/stage) for my ADC..Now I got few more doubts..i never seen anybody putting SOC(start of conversion pulse) and EOC(end of conversion pulse) in pipelined ADC..how to do that?..waiting for ur suggstions..
Regards

 

[maxwellequ]

Those signals are usually used in ADCs which have fs smaller than the operating frequency - ex: SAR ADCs. These ADCs sample after the SOC and take a number of clk cycles to end the conversion cycle. When they finish the EOC is activated and the output code is made available.

In pipeline ADCs there are output codes coming out in every clock cycle. In other words, in each clock cycle there is always a sampling operation and there are always bits coming out. The SOC/EOC do not make sense here.