Once the lower level partition is implemented use the createInterfaceLogic command to create the ILM:
createInterfaceLogic –dir partition_A.ilm
createInterfaceLogic extracts the information required for the ILM model and outputs it to the directory partition_A.ilm. If you look at the contents of this directory you will see the following. First, a sub-directory is created for each ILM type:
cts_data – ILM models for CTS
ilm_data – ILM models for setup analysis
si_ilm_data – ILM models for SI analysis
Under each of these directories the ILM data is stored. Each model include a DEF, SPEF, Verilog netlist and SDCs. For example:
partition_A_postRoute.core.sdc
partition_A_postRoute.def
partition_A_postRoute.spef
partition_A_postRoute.v
You need to run createInterfaceLogic for each partition you want to represent with an ILM.
Implementing the Top Level Using ILMs:
You can specify the ILMs when reading in the top level partition or after. To specify them while reading the configuration file (loadConfig) do one of the following:
Specifying ILMs through GUI when Loading Config File:
1. Select Design->Import Design…
2. On the Import Design form select Load. Load your top level config file.
3. On the Advanced Tab select ILM
4. Add an entry for each ILM:
Module: partition_A Dir: ../partition_A/partition_A.ilm
Module: partition_B Dir: ../partition_B/partition_B.ilm
5. Click OK to load the config file.
Specifying ILMs in the Config File:
set rda_Input(ui_ilmdir) "partition_A ../partition_A/partition_A.ilm partition_B ../partition_B/partition_B.ilm"
Specifying ILMs After Loading the Design:
Alternatively, you can specify the ILMs after reading in the top level partition instead of specifying the ILMs when loading the config file:
encounter> loadConfig dtmf_chip.conf
encounter> specifyILM –cell partition_A–dir ../partition_A/partition_A.ilm
encounter> specifyILM –cell partition_B –dir ../partition_B/partition_B.ilm
Once the ILMs are specified commands such as timeDesign, placeDesign, optDesign, etc. will automatically use these ILMs to represent the partitions. For example during placeDesign you would see the ILMs being read during flattenIlm:
Reading one ILM netlist ...
Backslashed names will retain backslash and a trailing blank character.
Keeping previous port order for module partition_A.
Reading verilog netlist '../partition_A/partition_A.ilm/ilm_data/partition_A/partition_A_postRoute.v'.
Reading one ILM netlist ...
Backslashed names will retain backslash and a trailing blank character.
Keeping previous port order for module partition_B.
Reading verilog netlist '../partition_B/partition_B/ilm_data/partition_B/partition_B_postRoute.v'.
…
Saving constraint mapping table*** Flattening ILM instance top/partition_A_INST ...
*** Flattening ILM instance top/partition_B_INST ...
…
*** Unflatten ILM (cpu=0:00:00.2 mem=239.3M) ***
Reference: Cadence website